r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1281

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

29.3.13 Control Data Assign Register (SICDAR)
SICDAR is a 16-bit readable/writable register that specifies the position of the control data in a
frame. SICDAR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't
care.).
Bit
7
6 to 4
3 to 0
Initial value:
Bit
15
14 to 12 —
R/W:
BIt:
Bit Name
RDRE
—
RDRA[3:0]
Bit Name
CD0E
CD0E
R/W
15
0
14
—
R
0
13
—
R
0
Initial
Value
0
All 0
0000
Initial
Value
0
All 0
12
—
R
0
R/W
R/W
R/W
R
R/W
R/W
R/W
R
11
0
R/W
CD0
10
0
A[3:0]
Receive Right-Channel Data Enable
Receive Right-Channel Data Assigns 3 to 0
Description
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value
should always be 0.
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Description
Control Channel 0 Data Enable
0: Disables transmission and reception of control
1: Enables transmission and reception of control
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
channel 0 data
channel 0 data
9
0
Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
R/W
8
0
CD1E
R/W
7
0
Rev. 1.00 Oct. 01, 2007 Page 1215 of 1956
—
R
6
0
Section 29 Serial I/O with FIFO (SIOF)
—
R
5
0
—
R
4
0
R/W
3
0
REJ09B0256-0100
R/W
CD1
2
0
A[3:0]
R/W
1
0
R/W
0
0