r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 899

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.21 Multicast Address Frame Receive Counter Register (MAFCR)
MAFCR is a 16-bit counter that indicates the number of frames received with a specified multicast
address. When the value in this register reaches H'0000FFFF, count-up is halted. This register is
cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in
ECMR is 0, this register is cleared to 0 by writing H'11111111.
Bit
31 to 16
15 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

MAFC[15:0] All 0
R/W
31
15

R
0
0
R/W
30
14

R
0
0
R/W
29
13

R
0
0
Initial
Value
All 0
R/W
28
12

R
0
0
R/W
27
11
R/W
R
R/W

R
0
0
R/W
26
10

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Multicast Address Frame Count
These bits indicate the number of multicast frames
received.
R/W
25

R
0
9
0
R/W
MAFC[15:0]
24

R
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
23

R
0
7
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 833 of 1956
22

R
0
6
0
R/W
21

R
0
5
0
R/W
20

R
0
4
0
R/W
19

R
0
3
0
REJ09B0256-0100
R/W
18

R
0
2
0
17

R
0
1
0
R/W
16

R
0
0
0