r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1126

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 27 Serial Communication Interface with FIFO (SCIF)
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of serial clock source: internal clock from baud rate generator or external clock from
• Four interrupt sources
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
• In asynchronous mode, modem control functions (SCIF0_RTS, SCIF1_RTS, SCIF0_CTS, and
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
• In asynchronous mode, a timeout error (DR) can be detected during reception.
Figure 27.1 shows a block diagram of the SCIF. Figures 27.2 to 27.6 show block diagrams of the
I/O ports in SCIF. There are two channels in this LSI. In figures 27.1 to 27.6, the channels are
omitted and explained.
Rev. 1.00 Oct. 01, 2007 Page 1060 of 1956
REJ09B0256-0100
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous
serial data transmission and reception.
SCIF_SCK0 or SCIF_SCK1 pin
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently.
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
consumption.
SCIF1_CTS) are provided.
the receive data in the receive FIFO register, can be ascertained.