r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1042

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 1.00 Oct. 01, 2007 Page 976 of 1956
REJ09B0256-0100
Interrupt
Transmit/
receive
interrupt for
port 0
(GEINT0)
Transmit/
receive
interrupt for
port 1
(GEINT1)
Interrupt Source
Receive Multicast Address Frame
Carrier Extension Error
Carrier Extension Loss
Receive Residual-Bit Frame
Receive Too-Long Frame
Receive Too-Short Frame
PHY-LSI Receive Error
CRC Error on Received Frame
Write-Back Completed
Transmit Underflow Frame Write-Back
Completed
Receive Overflow Frame Write-Back
Completed
Transmit Abort Detect
Receive Abort Detect
Receive Frame Counter Overflow
E-MAC Status Register Source
Frame Transmission Completed
Transmit Descriptor Empty
Transmit FIFO Underflow
Frame Reception
Receive Descriptor Empty
Receive FIFO Overflow
Carrier Loss Detection
Delayed Collision Detect
Register and Bit
EESR0.RMAF
EESR0.CEEF
EESR0.CELF
EESR0.RRF
EESR0.RTLF
EESR0.RTSF
EESR0.PRE
EESR0.CERF
EESR1.TWB
EESR1.TUC
EESR1.ROC
EESR1.TABT
EESR1.RABT
EESR1.RFCOF
EESR1.ECI
EESR1.TUC
EESR1.TDE
EESR1.TFUF
EESR1.FR
EESR1.RDE
EESR1.RFOF
EESR1.DLC
EESR1.CD
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
After write-back
When the interrupt
source is detected
When the interrupt
source is detected
After write-back
When the interrupt
source is detected
When the interrupt
source is detected
After write-back
When the interrupt
source is detected
When the interrupt
source is detected
When the interrupt
source is detected
When the interrupt
source is detected
Interrupt Generated
Timing

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