r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 361

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.4.4
On-chip module interrupts are interrupts generated by on-chip modules. Not every interrupt source
is assigned a different interrupt vector, but sources are reflected in the interrupt event register
(INTEVT), so it is easy to identify sources by using the INTEVT value as a branch offset in the
exception handling routine.
A priority level from 31 to 0 can be set for each module by means of INT2PRI0 to INT2PRI13.
The INTC rounds off the lowest one bit and sends 4-bit code to the CPU. In detail, see section
9.4.5, Interrupt Priority Level of On-chip Module Interrupts.
When the INTMU bit in the CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically modified to the level 15 of the accepted NMI interrupt. When the INTMU bit in
CPUOPM is cleared to 0, the IMASK value in SR is not affected by the accepted NMI interrupt.
Updating of the interrupt source flag and interrupt enable flag of a peripheral module should only
be carried out when the BL bit in SR is set to 1 or while the corresponding interrupt does not occur
by setting its mask bit. To prevent erroneous interrupt acceptance from an interrupt source that
should have been updated, first read the on-chip peripheral register containing the relevant flag
and wait the priority determination time shown in table 9.8, then clear the BL bit to 0. This will
secure the necessary timing internally. When updating a number of flags, there is no problem if
only the register containing the last flag updated is read from.
If flag updating is performed while the BL bit is cleared to 0, the program may jump to the
interrupt handling routine when the INTEVT value is 0. In this case, interrupt processing is
initiated due to the timing relationship between the flag update and interrupt request recognition
within this LSI. Processing can be continued without any problem by executing an RTE
instruction.
9.4.5
When an on-chip module interrupt is generated, the INTC outputs its interrupt exception code
(INTEVT code) as individual source identification to the CPU. When the CPU accepts an
interrupt, the corresponding INTEVT code is indicated in INTEVT. Even if the interrupt source
register of the INTC is not read, the interrupt source can be identified by reading INTEVT of the
CPU in the interrupt handler. Table 9.1 lists the source of on-chip module interrupt and the
interrupt exception codes.
On-chip module interrupt, it can be set individual interrupt sources to 30 (5-bit) priority levels (see
figure 9.1). The interrupt level receive interface consists of four bits and there are 15 priority
levels (H'0 is interrupt request mask). The INTC consists of five bits in which one bit is extended
On-chip Module Interrupts
Interrupt Priority Level of On-chip Module Interrupts
Rev. 1.00 Oct. 01, 2007 Page 295 of 1956
Section 9 Interrupt Controller (INTC)
REJ09B0256-0100