r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 124

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 3 Instruction Set
T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a
conditional branch instruction. An example of the use of a conditional branch instruction is shown
below.
ADD
CMP/EQ R1, R0
BT
In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is
used before modification, and in data access, the MD bit is accessed after modification. The other
bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction
execution. The STC and STC.L SR instructions access all SR bits after modification.
Constant Values: An 8-bit constant value can be specified by the instruction code and an
immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in
memory, and can be referenced by a PC-relative load instruction.
MOV.W @(disp, PC), Rn
MOV.L
There are no PC-relative load instructions for floating-point operations. However, it is possible to
set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point
register.
Rev. 1.00 Oct. 01, 2007 Page 58 of 1956
REJ09B0256-0100
#1, R0
TARGET ; Branches to TARGET if T bit = 1 (R0 = R1)
@(disp, PC), Rn
; T bit is not changed by ADD operation
; If R0 = R1, T bit is set to 1