r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1628

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 36 USB Function Controller (USBF)

• Data Stage (Control-In)

The application first analyzes command data from the host in the setup stage, and determines the

subsequent data stage direction. If the result of command data analysis is that the data stage is in-

transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be

sent, this data is written to the FIFO after the data written first has been sent to the host

(IFR0/EP0i TS = 1).

The end of the data stage is identified when the host transmits an OUT token and the status stage

Note: If the size of the data transmitted by the function is smaller than the data size requested by

Rev. 1.00 Oct. 01, 2007 Page 1562 of 1956

REJ09B0256-0100

the host, the function indicates the end of the data stage by returning to the host a packet

shorter than the maximum packet size. If the size of the data transmitted by the function is

an integral multiple of the maximum packet size, the function indicates the end of the data

stage by transmitting a zero-length packet.

Data transmission to host

Set EP0i transmission

(IFR0/EP0i TS = 1)

IN token reception

USB function

in EP0i FIFO?

complete flag

Figure 36.6 Data Stage (Control-In) Operation

Interrupt request

Clear EP0i transmission

data register (EPDR0i)

Write 1 to EP0i packet

(TRG/EP0i PKTE = 1)

(IFR0/EP0i TS = 0)

Write data to EP0i

From setup stage

complete flag