r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1296

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
(2)
Figure 29.10 shows an example of settings and operation for master mode reception.
Rev. 1.00 Oct. 01, 2007 Page 1230 of 1956
REJ09B0256-0100
No.
5
6
2
4
7
8
1
3
Reception in Master Mode
Store SIOFRXD receive data in SIRDR
SIRDAR, SICDAR, and SIFCTR
synchronously with SIOF_SYNC
Clear the RXE bit in SICTR to 0
Set the SCKE bit in SICTR to 1
Set the FSE and RXE bits
Start SIOFSCK output
Set SIMDR, SISCR,
Figure 29.10 Example of Receive Operation in Master Mode
in SICTR to 1
RDREQ = 1?
Read SIRDR
Flow Chart
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for receive data,
slot position for control data, and
FIFO request threshold value
Set operation start for baud rate
generator
Set the start for frame synchronous
signal output and enable
reception
Read receive data
Set to disable reception
SIOF Settings
Output serial clock
Output frame synchronous
signal
Issue receive transfer
request according to the
receive FIFO threshold
value
Reception
End reception
SIOF Operation