r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1085

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

(3)
(a)
• Timing chart
• Active level setting for ST_STRB, ST_START, ST_VALID, and ST_REQ pins
• Selection of ST_REQ pin usage
(b) Receive Packet Length
The receive packet length can be selected from 188 and 192 bytes.
(c)
The size of the work area in external memory can be selected from among 0, 16, 32, and 48 bytes.
Figure 25.4 shows the timing of the strobe reception interface.
The active levels of the ST_STRB, ST_START, ST_VALID, and ST_REQ pins can be set by
the STRB, STAT, VLD, and REQ bits in STIMDR, respectively.
Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR.
When usage of the ST_REQ pin is enabled, the ST_REQ pin is asserted when the free space in
the transmit/receive FIFO for stream data becomes eight bytes or less. After assertion, up to
eight bytes of data can be received. The ST_REQ pin is negated when the free space in the
FIFO has become 192 bytes or more.
When usage of the ST_REQ pin is disabled, the ST_REQ pin output is fixed at low or high
depending on the REQ bit value.
Strobe Reception
Strobe Reception Interface
Work Area
ST_STRB (input)
ST_START (input)
ST_VALID (input)
ST_REQ (output)
ST_D7 to ST_D0
(input)
Figure 25.4 Strobe Reception Timing
Up to 8 bytes can be received
Rev. 1.00 Oct. 01, 2007 Page 1019 of 1956
Section 25 Stream Interface (STIF)
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REJ09B0256-0100