r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 747

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

18.7
18.7.1
To preserve the contents of the DDR-SDRAM with battery backup, make sure that the DDR-
SDRAM is in the self-refresh mode before turning off the system power supply. When the system
power supply is turned on, initialization of the DDR-SDRAM or cancellation of the self-refresh
mode must be performed according to whether the DDR-SDRAM has been in self-refresh mode or
has not been initialized. For DDR-SDRAM, both a transition to and a cancellation of the self-
refresh mode are done by issuing a command.
(1)
Bit 33 in the MIM register. The initial value is 0. Setting this bit to 1 after setting the DRE bit in
MIM to 1 causes the DDRIF to start the sequence for a transition to the self-refresh mode. For
details, see section 12.5.5 (1), Self-Refresh Mode.
(2)
Bits 2 to 0 in the SCR register. These bits are used to assert the M_CKE signal (high) by setting
SMS = B'011 when canceling the self-refresh mode with the DESL command.
(3)
To prevent the M_CKE signal from being unstable when turning on or off the LSI power supply,
the M_BKPRST signal must be input in synchronization with turning the LSI power supply on or
off. The M_BKPRST signal must be kept low while the system power supply is turned off.
RMODE Bit
Bits SMS2 to SMS0
M_BKPRST Signal
DDR-SDRAM Power Supply Backup
Control of Self-Refresh and Initialization
Rev. 1.00 Oct. 01, 2007 Page 681 of 1956
Section 18 Power-Down Mode
REJ09B0256-0100