r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 173

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

5.2.2
The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code
set in EXPEVT is that for a reset or general exception event. The exception code is set
automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
Initial value:
Initial value:
Bit
31 to 12 
11 to 0
R/W:
R/W:
Bit:
Bit:
Exception Event Register (EXPEVT)
Bit Name
EXPCODE
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
H'000 or
H'020
28
12
R
R
0
0
R/W
27
11
R
0
0
R/W
R
R/W
R/W
26
10
R
0
0
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Exception Code
The exception code for a reset or general exception is
set. For details, see table 5.3.
R/W
25
R
0
9
0
R/W
24
R
0
8
0
R/W
23
R
0
7
0
EXPCODE
Rev. 1.00 Oct. 01, 2007 Page 107 of 1956
R/W
22
R
0
6
0
R/W
0/1
21
R
0
5
Section 5 Exception Handling
R/W
20
R
0
4
0
R/W
19
R
0
3
0
REJ09B0256-0100
R/W
18
R
0
2
0
R/W
17
R
0
1
0
R/W
16
R
0
0
0