r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 64

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Table 37.3
Table 37.4
Table 37.5
Table 37.6
Table 37.7
Table 37.8
Section 38 A/D Converter
Table 38.1
Table 38.2
Table 38.3
Table 38.4
Table 38.5
Table 38.6
Section 39 D/A Converter (DAC)
Table 39.1
Table 39.2
Table 39.3
Section 40 General Purpose I/O (GPIO)
Table 40.1
Table 40.2
Table 40.3
Section 41 User Break Controller (UBC)
Table 41.1
Table 41.2
Table 41.3
Table 41.4
Section 42 User Debugging Interface (H-UDI)
Table 42.1
Table 42.2
Table 42.3
Table 42.4
Table 42.5
Table 42.6
Section 43 Electrical Characteristics
Table 43.1
Table 43.2
Rev. 1.00 Oct. 01, 2007 Page lxiv of lxvi
Register State in Each Operating Mode.................................................................. 83
I/O Clock Frequency and Clock Division Ratio ..................................................... 86
Limits on the Resolution of Rotated Displays, Burst Length, and Connected
Memory (32-bit SDRAM) .................................................................................... 119
Available Power-Supply Control-Sequence Periods at Typical Frame Rates....... 130
LCDC Operating Modes....................................................................................... 131
LCD Module Power-Supply States....................................................................... 131
Pin Configuration................................................................................................ 1643
Register Configuration........................................................................................ 1644
Register State in Each Operating Mode.............................................................. 1644
Analog Input Channels and A/D Data Registers................................................. 1645
A/D Conversion Time......................................................................................... 1654
Relationship between Clock Division Ratio and Usable Pck0 Clock Frequency1658
Pin Configuration................................................................................................ 1660
Register Configuration........................................................................................ 1660
Register State in Each Operating Mode.............................................................. 1660
Multiplexed Pins Controlled by Port Control Registers ......................................... 80
Register Configuration (1) ...................................................................................... 90
Register States in Each Operating Mode ................................................................ 92
Register Configuration........................................................................................ 1747
Register Status in Each Processing State ............................................................ 1748
Settings for Match Data Setting Register............................................................ 1762
Relation between Operand Sizes and Address Bits to be Compared .................. 1771
Pin Configuration................................................................................................ 1785
Commands Supported by Boundary-Scan TAP Controller ................................ 1787
Register Configuration (1) .................................................................................. 1788
Register Configuration (2) .................................................................................. 1788
Register Status in Each Processing State ............................................................ 1788
SDBSR Configuration ........................................................................................ 1792
Absolute Maximum Ratings ................................................................................... 79
Power-On and Power-Off Timing .......................................................................... 81