r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1104

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 26 I
26.3.6
The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective
status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate
bit position.
Rev. 1.00 Oct. 01, 2007 Page 1038 of 1956
REJ09B0256-0100
Bit
7
6
5
4
Master Status Register (ICMSR)
2
C Bus Interface (IIC)
Bit Name
—
MNR
MAL
MST
Initial value:
R/W:
Initial Value
0
0
0
0
BIt:
R
7
0
−
R/W* R/W* R/W* R/W* R/W* R/W* R/W*
MNR
6
0
R/W
R
R/W*
R/W*
R/W*
MAL
5
0
MST
Description
Reserved
The write value should always be 0.
Master Nack Received
When this bit is set to 1, this bit indicates that
the master has received a nack response (the
SDA line is high during the acknowledge cycle
on the bus) to either an address or data
transmission.
Master Arbitration Lost
In a multi-master system, when this bit is set to
1, it indicates that the master has lost
arbitration to one of other masters on the bus.
At this point, MIE is reset and the master
interface is disabled.
Master Stop Transmitted
When this bit is set to 1, it indicates that the
master has sent a STOP condition on the bus.
A STOP condition can be sent either as a
result of the setting of the forced stop bit in the
control register, or from a nack being received
from a slave during a slave receive data
packet.
4
0
MDE
3
0
MDT
2
0
MDR
1
0
MAT
0
0