r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 501

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

The DDRIF is supported only when the clock ratio between the SuperHyway bus clock and the

external memory clock is 1:1 (DDR266 or DDR200). The maximum operating frequency for the

SuperHyway bus is 133 MHz. The minimum operating frequency depends on the DDR-SDRAM

clock frequency. Therefore see the DDR-SDRAM datasheet.

The clock supplied to the DDRIF is stopped in the following three modes:

• DDR-SDRAM power supply backup mode

• Software standby mode

• RTC power supply backup mode

Since the clock is not supplied in the above cases, auto-refreshing is not performed. As a result,

the refresh cycle is not held and then the DDR-SDRAM data will be damaged. To prevent this, the

DDR-SDRAM should enter the self-refresh state through software before the clock supply is

stopped. For details on entering/canceling the self-refresh mode, see section 12.5.5 (1), Self-

Refresh Mode.

This memory controller automatically opens the DDR-SDRAM bank by memory access

(read/write). When issuing the REFA command with the SMS bits in SCR, be sure to close the

bank by issuing the PREALL command with the SMS bits in SCR. This operation is also

necessary when SCR is used to perform concentrated refresh (REFA) on all rows in the memory

before self-refresh operations.

12.5.10 Note on Timing of Connected DDR-SDRAM

This memory controller only supports memory in which the number of cycles (tRAP) required

from issuing an ACT command to issuing a read or write with auto-precharge command and the

number of cycles (tRDC) required from issuing an ACT command to issuing a read or write

command are the same. If the two numbers differ, the DDR-SDRAM should be accessed in bank-

Operating Frequency

Note on Clock Stop

Using SCR to Issue REFA Commands (Outside the Initialization Sequence)

Section 12 DDR-SDRAM Interface (DDRIF)

Rev. 1.00 Oct. 01, 2007 Page 435 of 1956

REJ09B0256-0100