r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 268

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 7 Caches

When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable

area, the instruction cache operates as follows:

1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual

2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting

• If there is a way whose tag matches and the V bit is 1, see No. 3.

• If there is no way whose tag matches and the V bit is 1, see No. 4.

3. Cache hit

4. Cache miss

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address bits [12:5].

from virtual address translation by the MMU:

The data indexed by virtual address bits [4:2] is read as an instruction from the data field on

the hit way. The LRU bits are updated to indicate the way is the latest one.

Data is read into the cache line on the way which selected using LRU bits to replace from the

physical address space corresponding to the virtual address. Data reading is performed, using

the wraparound method, in order from the quad-word data (8 bytes) including the cache-

missed data, and when the corresponding data arrives in the cache, the read data is returned to

the CPU as an instruction. While the remaining one cache line of data is being read, the CPU

can execute the next processing. When reading of one line of data is completed, the tag

corresponding to the physical address is recorded in the cache, and 1 is written to the V bit, the

LRU bits are updated to indicate the way is the latest one.

Instruction Cache Operation

Read Operation