r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 180

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 5 Exception Handling

A priority ranking is provided for all exceptions for use in determining which of two or more

simultaneously generated exceptions should be accepted. Five of the general exceptions—general

illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot

FPU disable exception, and unconditional trap exception—are detected in the process of

instruction decoding, and do not occur simultaneously in the instruction pipeline. These

exceptions therefore all have the same priority. General exceptions are detected in the order of

instruction execution. However, exception handling is performed in the order of instruction flow

(program order). Thus, an exception for an earlier instruction is accepted before that for a later

instruction. An example of the order of acceptance for general exceptions is shown in figure 5.2.

Rev. 1.00 Oct. 01, 2007 Page 114 of 1956

REJ09B0256-0100

Pipeline flow:

Order of detection:

Order of exception handling:

Exception Source Acceptance

Instruction n

Instruction n + 1

Instruction n + 2

Instruction n + 3

General illegal instruction exception (instruction n + 1) and

TLB miss (instruction n + 2) are detected simultaneously

TLB miss (instruction n)

Re-execution of instruction n

General illegal instruction exception

(instruction n + 1)

Re-execution of instruction n + 1

TLB miss (instruction n + 2)

Re-execution of instruction n + 2

Execution of instruction n + 3

Figure 5.2 Example of General Exception Acceptance Order

TLB miss (instruction access)

General illegal instruction exception

TLB miss (data access)

Program order

E1, E2, E3 : Instruction execution

Instruction fetch

Instruction decode

Memory access)