r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1142

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 27 Serial Communication Interface with FIFO (SCIF)
Notes: x: Don't care
Rev. 1.00 Oct. 01, 2007 Page 1076 of 1956
REJ09B0256-0100
Bit
1
0
1. Outputs a clock with a frequency 16 times the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
Bit Name
CKE1
CKE0
Initial
Value
0
0
R/W
R/W
R/W
Description
Clock Enable 1, 0
These bits select the SCIF clock source and whether to
enable or disable the clock output from the SCIF_SCK
pin. The CKE1 and CKE0 bits are used together to
specify whether the SCIF_SCK pin functions as a serial
clock output pin or a serial clock input pin. Note
however that the CKE0 bit setting is valid only when an
internal clock is selected as the SCIF clock source
(CKE1 = 0). When an external clock is selected (CKE1
= 1), the CKE0 bit setting is invalid. The CKE1 and
CKE0 bits must be set before determining the SCIF's
operating mode with SCSMR.
00: Internal clock/SCIF_SCK pin functions as port
01: Internal clock/SCIF_SCK pin functions as
1x: External clock/SCIF_SCK pin functions as
0x: Internal clock/SCIF_SCK pin functions as
1x: External clock/SCIF_SCK pin functions as
Asynchronous mode
Clocked synchronous mode
clock output*
clock input*
synchronization clock output
synchronization clock input
2
1

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