r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1033

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
FIFO to the receive buffer. For restarting frame reception from the GMII/MII/RMII, when the E-
DMAC resumes frame reception from the GMII/MII/RMII, it only accepts from the start of the
frame.
(c)
Flow Control
When the amount of receive data or the number of receive frames in the receive FIFO leads to one
of the following conditions, the E-DMAC notifies the E-MAC to control E-MAC writing to the
receive FIFO.
• When the space used in the receive FIFO exceeds the data amount specified by FCFTR
• When the number of receive frames in the receive FIFO exceeds the value specified by FCFTR
The threshold of the receive data amount can be set in a range from 256 to 65536 bytes in 256-
byte units.
The threshold of receive frames can be set in a range from 1 to 24 frames (by the frame) in frame
units.
(d) Receive Descriptor Empty
When the RACT bit of the read descriptor is 0 (invalid), the receive descriptor empty state is
determined and DMA transfer is stopped. Then the following operation is performed.
• Writes the RR bit in EDRRR to 0
• Sets the RDE bit in EESR to 1 and generates an interrupt to the CPU.
To resume the DMA transfer to the receive buffer, the interrupt source needs to be cleared by
software, the receive descriptor needs to be re-set and the RR bit in EDRRR should be set to 1.
Even if receive descriptor is empty, frame reception from the GMII/MII/RMII to the receive FIFO
is continued if there is empty space left in the receive FIFO and receive frame information
management area. Therefore, even if a receive descriptor empty state is determined, the DMA
transfer can be performed without discarding the frames received from the GMII/MII/RMII if
DMA transfer to the receive buffer can be resumed before an overflow occurs.
Rev. 1.00 Oct. 01, 2007 Page 967 of 1956
REJ09B0256-0100