C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet
C8051T627-B-GM
Specifications of C8051T627-B-GM
Related parts for C8051T627-B-GM
C8051T627-B-GM Summary of contents
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Analog Peripherals - 10-Bit ADC (‘T620/6/7 and ‘T320/1 only) • 500 ksps • external inputs • VREF from on-chip VREF, external pin, Internal 1.8 V Regulator • Internal or external start of ...
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C8051T620/1/6/7 & C8051T320/1/2/3 2 Rev. 1.2 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table of Contents 1. System Overview ..................................................................................................... 15 2. Ordering Information ............................................................................................... 21 3. Pin Definitions.......................................................................................................... 22 4. LQFP-32 Package Specifications ........................................................................... 28 5. QFN-32 Package Specifications ............................................................................. 30 6. QFN-28 Package Specifications ............................................................................. 32 7. Electrical ...
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C8051T620/1/6/7 & C8051T320/1/2/3 15.2.1.2. Bit Addressable Locations .............................................................. 90 15.2.1.3. Stack ............................................................................................ 90 15.2.2. External RAM .......................................................................................... 91 15.2.3. Accessing USB FIFO Space ................................................................... 91 16. Special Function Registers................................................................................... 95 17. Interrupts .............................................................................................................. 101 17.1. MCU Interrupt Sources and Vectors.............................................................. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.6. External Oscillator Drive Circuit..................................................................... 134 21.6.1. External Crystal Mode........................................................................... 134 21.6.2. External RC Example............................................................................ 136 21.6.3. External Capacitor Example.................................................................. 136 22. Port Input/Output ................................................................................................. 138 22.1. Port I/O Modes of Operation.......................................................................... 139 22.1.1. Port Pins Configured ...
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C8051T620/1/6/7 & C8051T320/1/2/3 24.3.1. Transmitter Vs. Receiver....................................................................... 196 24.3.2. Arbitration.............................................................................................. 196 24.3.3. Clock Low Extension............................................................................. 196 24.3.4. SCL Low Timeout.................................................................................. 196 24.3.5. SCL High (SMBus Free) Timeout ......................................................... 197 24.4. Using the SMBus........................................................................................... 197 24.4.1. SMBus Configuration Register.............................................................. 197 24.4.2. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 28. Timers ................................................................................................................... 246 28.1. Timer 0 and Timer 1 ...................................................................................... 248 28.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 248 28.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 249 28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 249 28.1.4. Mode 3: ...
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C8051T620/1/6/7 & C8051T320/1/2/3 List of Figures Figure 1.1. C8051T620/1 Block Diagram ................................................................ 16 Figure 1.2. C8051T626/7 Block Diagram ................................................................ 17 Figure 1.3. C8051T320/2 Block Diagram ................................................................ 18 Figure 1.4. C8051T321/3 Block Diagram ................................................................ 19 Figure 1.5. Typical Bus-Powered Connections ....................................................... ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Figure 20.2. Power-On and VDD Monitor Reset Timing ....................................... 122 Figure 21.1. Oscillator Options .............................................................................. 127 Figure 21.2. External Crystal Example .................................................................. 135 Figure 22.1. Port I/O Functional Block Diagram .................................................... 138 Figure 22.2. Port I/O Cell ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Figure 27.11. SPI Slave Timing (CKPHA = 1) ....................................................... 244 Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 249 Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 250 Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 251 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 List of Tables Table 2.1. Product Selection Guide ......................................................................... 21 Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3 ................ 22 Table 7.1. Absolute Maximum Ratings .................................................................... 34 Table 7.2. Global Electrical Characteristics ............................................................. 35 Table 7.3. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 List of Registers SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 49 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 50 SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 50 SFR Definition 8.4. ADC0CN: ADC0 Control ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control ................................... 133 SFR Definition 21.6. OSCXCN: External Oscillator Control ........................................ 137 SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 .......................................... 147 SFR Definition 22.2. XBR1: Port I/O Crossbar ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 28.2. TCON: Timer Control ................................................................. 252 SFR Definition 28.3. TMOD: Timer Mode ................................................................... 253 SFR Definition 28.4. TL0: Timer 0 Low Byte ............................................................... 254 SFR Definition 28.5. TL1: Timer 1 Low Byte ............................................................... 254 SFR ...
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C8051T620/1/6/7 & C8051T320/1/2/3 1. System Overview C8051T620/1/6/7 & C8051T320/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. High-speed pipelined 8051-compatible microcontroller core ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte OTP Program Memory C2CK/RST Debug / Programming Hardware 256 Byte SRAM C2D 1024 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator GND ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Power On CIP-51 8051 Reset Controller Core Reset 64/32k Byte OTP Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 3072 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator Core ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte OTP Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 1024 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator GND ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Power On CIP-51 8051 Reset Controller Core Reset 16k Byte OTP Program Memory Debug / C2CK/RST Programming Hardware 256 Byte SRAM C2D 1024 Byte XRAM In-system Programming Hardware VPP Peripheral Power Voltage REGIN Regulator VDD Regulator Core ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SUPPLY NET Add decoupling/bypass 4.7µF capacitors close to each voltage supply pin. USB Add ESD protection diodes designed for use with USB, such as Littlefuse SP0503BAHT or equivalent. Keep the USB shield ground isolated from the device ...
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... C8051T620/1/6/7 & C8051T320/1/2/3 2. Ordering Information Table 2.1. Product Selection Guide 1 C8051T620-GM 48 16k 1280 Y 1 C8051T621-GM 48 16k 1280 C8051T626-B-GM 48 64k 3328 Y 5 C8051T627-B-GM 48 32k 3328 C8051T320-GQ 48 16k 1280 C8051T321-GM 48 16k 1280 C8051T322-GQ 48 16k 1280 C8051T323-GM 48 16k 1280 Y Notes: 1 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3 Pin Number Name ‘T62x ‘T320/2 ‘T321 GND RST C2CK P3. C2D ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3(Continued) Pin Number Name ‘T62x ‘T320/2 ‘T321/3 P0. XTAL2 P0 P0 P0. CNVSTR P0. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3(Continued) Pin Number Name ‘T62x ‘T320/2 ‘T321/3 P1 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 P0.1 1 P0.0 2 GND C8051T620/1/6/7-GM Top View D- 5 VIO 6 VDD 7 GND (optional) REGIN 8 Figure 3.1. QFN-32 Pinout Diagram (Top View Rev. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 1 P0.1 2 P0.0 3 GND C8051T320/2- VDD REGIN 7 VBUS 8 Figure 3.2. LQFP-32 Pinout Diagram (Top View) 26 Top View Rev. 1.2 24 P1.2 23 P1.3 22 P1.4 P1.5 / ...
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C8051T620/1/6/7 & C8051T320/1/2/3 P0.1 1 P0.0 2 GND 3 C8051T321/3- Top View D- 5 VDD 6 GND (optional) REGIN 7 Figure 3.3. QFN-28 Pinout Diagram (Top View) 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 / ...
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C8051T620/1/6/7 & C8051T320/1/2/3 4. LQFP-32 Package Specifications Figure 4.1. LQFP-32 Package Drawing Table 4.1. LQFP-32 Package Dimensions Dimension Min Typ A — — A1 0.05 — A2 1.35 1.40 b 0.30 0.37 c 0.09 — D 9.00 BSC. D1 7.00 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Figure 4.2. LQFP-32 Recommended PCB Land Pattern Table 4.2. LQFP-32 PCB Land Pattern Dimensions Dimension Min Max C1 8.40 8.50 C2 8.40 8.50 E 0.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise ...
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C8051T620/1/6/7 & C8051T320/1/2/3 5. QFN-32 Package Specifications Figure 5.1. QFN-32 Package Drawing Table 5.1. QFN-32 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 5.00 BSC. D2 3.20 3.30 e 0.50 BSC. E 5.00 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Figure 5.2. QFN-32 Recommended PCB Land Pattern Table 5.2. QFN-32 PCB Land Pattern Dimensions Dimension Min Max C1 4.80 4.90 C2 4.80 4.90 E 0.50 BSC X1 0.20 0.30 Notes: General 1. All dimensions shown are in ...
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C8051T620/1/6/7 & C8051T320/1/2/3 6. QFN-28 Package Specifications Figure 6.1. QFN-28 Package Drawing Table 6.1. QFN-28 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.25 REF b 0.18 0.23 D 5.00 BSC. D2 2.90 3.15 e 0.50 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Figure 6.2. QFN-28 Recommended PCB Land Pattern Table 6.2. QFN-28 PCB Land Pattern Dimensions Dimension Min Max C1 4.80 C2 4.80 E 0.50 X1 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless ...
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C8051T620/1/6/7 & C8051T320/1/2/3 7. Electrical Characteristics 7.1. Absolute Maximum Specifications Table 7.1. Absolute Maximum Ratings Parameters Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin (except V during program- PP ming) with respect to GND ...
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C8051T620/1/6/7 & C8051T320/1/2/3 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameters Supply Voltage (Note 1) Regulator1 in Normal Mode Regulator1 in Bypass Mode Digital Supply Current with CPU ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.3. Port I/O DC Electrical Characteristics V = 1 < –40 to +85 °C unless otherwise specified Parameters Test Condition Output High Voltage I = –10 µA, ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.5. Internal Voltage Regulator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameters Voltage Regulator (REG0 Input Voltage Range 2 Output Voltage (V ) Output Current = 1 to 100 ...
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... C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.6. EPROM Electrical Characteristics Parameters EPROM Size (Note 1) C8051T620/1 & C8051T320/1/2/3 C8051T626 C8051T627 Write Cycle Time (per Byte) (Note 2) In-Application Program- Capacitor on V ming Write Cycle Time discharged (per Byte) Capacitor on V (Note 3) tially charged to 3.3 V Programming Voltage ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameters Oscillator Frequency OSCLD = 11b Oscillator Supply Current ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.10. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, DD Parameters DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.11. Temperature Sensor Electrical Characteristics V – +85 °C unless otherwise specified. DD Parameters Linearity Slope Slope Error* Offset Temp = 0 °C Offset Error* Temp = 0 °C Note: Represents ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.13. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameters Response Time: CP0+ – CP0– = 100 mV * Mode 0, Vcm = 1.5 V CP0+ – CP0– = ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 7.14. USB Transceiver Electrical Characteristics 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Transmitter Output High Voltage ( Output Low Voltage ( Output Crossover ...
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C8051T620/1/6/7 & C8051T320/1/2/3 7.3. Typical Performance Curves 12.0 10.0 8.0 6.0 4.0 2.0 0 Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8. 10-Bit ADC (ADC0, C8051T620/6/7 and C8051T320/1 Only) ADC0 on the C8051T620/6/7 and C8051T320 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a programmable window ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8.3.2. Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 8.8. ADC0LTL: ADC0 Less-Than ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8.4.1. Window Detector Example Figure 8.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by ...
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C8051T620/1/6/7 & C8051T320/1/2/3 8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only) ADC0 on the C8051T620/6/7 and C8051T320/1 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select Bit 7 6 Name R R Type 1 0 Reset SFR Address = 0xBB Bit Name 7:5 Unused Read = 100b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive ...
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C8051T620/1/6/7 & C8051T320/1/2/3 9. Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only) An on-chip temperature sensor is included on the C8051T620/6/7 and C8051T320/1 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 9.1. Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 7.11 on page 41 for specifications). For absolute temperature measurements, offset and/or gain calibration is recommended. A single-point ...
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C8051T620/1/6/7 & C8051T320/1/2/3 10. Voltage Reference Options The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer- ence, the on-chip reference voltage generator routed to the VREF pin, the unregulated power supply volt- age ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 10.1. REF0CN: Reference Control Bit 7 6 REFBGS Name R/W R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7 REFBGS Reference Buffer Gain Select. This bit selects between 1x and 2x gain ...
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C8051T620/1/6/7 & C8051T320/1/2/3 11. Voltage Regulators (REG0 and REG1) C8051T620/1/6/7 & C8051T320/1/2/3 devices include two internal voltage regulators: one regulates a volt- age source on REGIN to 3.45 V (REG0), and the other regulates the internal core supply to 1.8 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 VBUS From VBUS From 5 V REGIN Power Net VDD Power Net Figure 11.2. REG0 Configuration: USB Self-Powered VBUS From VBUS REGIN From 3 V Power Net Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator ...
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C8051T620/1/6/7 & C8051T320/1/2/3 VBUS From 5 V REGIN Power Net VDD Power Net Figure 11.4. REG0 Configuration: No USB Connection VBUS Sense Voltage Regulator (REG0 Out Rev. 1.2 Device Power Net 63 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 11.2. Voltage Regulator (REG1) Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode. This allows any enabled reset source to generate a reset for the device and bring the device ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 11.1. REG01CN: Voltage Regulator Control Bit 7 6 REG0DIS VBSTAT Reserved Name R/W R Type 0 0 Reset SFR Address = 0xC9 Bit Name 7 REG0DIS Voltage Regulator (REG0) Disable. This bit enables or disables ...
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C8051T620/1/6/7 & C8051T320/1/2/3 12. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family ...
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... This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or other on-chip resources. C2 details can be found in Section “30. C2 Interface” on page 288. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro- vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys- tem device programming and debugging ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic ORL A, direct OR direct byte to A ORL A, @Ri OR indirect RAM to A ORL A, #data OR immediate to A ORL direct direct ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic MOV DPTR, #data16 Load DPTR with 16-bit constant MOVC A, @A+DPTR Move code byte relative DPTR to A MOVC A, @A+PC Move code byte relative MOVX A, ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 12.1. CIP-51 Instruction Set Summary(Continued) Mnemonic RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR JZ ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to ...
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C8051T620/1/6/7 & C8051T320/1/2/3 12.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 12.3. SP: Stack Pointer Bit 7 6 Name Type Reset 0 0 SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 12.6. PSW: Program Status Word Bit 7 6 Name CY AC Type R/W R/W Reset 0 0 SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last ...
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C8051T620/1/6/7 & C8051T320/1/2/3 13. Prefetch Engine The C8051T620/1/6/7 & C8051T320/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch ...
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C8051T620/1/6/7 & C8051T320/1/2/3 14. Comparator0 and Comparator1 C8051T620/1/6/7 & C8051T320/1/2/3 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 14.1, Comparator1 is shown in Figure 14.2. The two comparators operate identically with the following exceptions: (1) Their ...
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C8051T620/1/6/7 & C8051T320/1/2/3 CP1 + Comparator CP1 - Input Mux CPT1MD Figure 14.2. Comparator1 Functional Block Diagram The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a ...
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C8051T620/1/6/7 & C8051T320/1/2/3 CPn+ VIN+ + CPn CPn- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 14.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.3. CPT1CN: Comparator1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. 6 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9C Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP1RIE Comparator1 Rising-Edge ...
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C8051T620/1/6/7 & C8051T320/1/2/3 14.1. Comparator Multiplexers C8051T620/1/6/7 & C8051T320/1/2/3 devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator inputs are selected in the CPTnMX registers (SFR Definition 14.5 and SFR Definition 14.6). ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[2:0] Name R Type 0 0 Reset SFR Address = 0x9F Bit Name 7 Unused Read = 0b; Write = don’t care. 6:4 CMX0N[2:0] Comparator0 Negative Input ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection Bit 7 6 CMX1N[2:0] Name R Type 0 0 Reset SFR Address = 0x9E Bit Name 7 Unused Read = 0b; Write = don’t care. 6:4 CMX1N[2:0] Comparator1 Negative Input ...
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C8051T620/1/6/7 & C8051T320/1/2/3 15. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same ...
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... C8051T620/1/6/7 & C8051T320/1/2/3 PROGRAM/DATA MEMORY (EPROM) C8051T627 0xFFFF RESERVED 0x8000 0x7FFF 32k Bytes EPROM Memory 0x0000 C8051T626 0xFFFF RESERVED 0xFE00 0xFDFF 64k Bytes EPROM Memory 0x0000 Figure 15.2. C8051T626/7 Memory Map 15.1. Program Memory The CIP-51 core has program memory space. The C8051T620/1/6/7 & C8051T320/1/2/3 imple- ments up to 65535 bytes of this program memory space as in-system byte-programmable EPROM ...
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... Section “9.1. Calibration” on page 58. 15.1.3. Serialization All C8051T620/1/6/7 & C8051T320/1/2/3 devices have a factory serialization located in EPROM memory. This value is unique to each device. The serial number is located at the address indicated in Figure 15.3 and can be accessed like any constant array in program memory. C8051T627 0xFFFF Serial Number 0xFFFC 0xFFFB ...
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C8051T620/1/6/7 & C8051T320/1/2/3 15.2. Data Memory The C8051T620/1 and C8051T320/1/2/3 device family includes 1280 bytes of RAM data memory, while the C8051T626/6 devices include 3328 bytes. 256 bytes of this memory is mapped into the internal RAM space of the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 15.2.2. External RAM There are 1024 bytes (C8051T620/1/320/1/2/3 devices) or 3072 bytes (C8051T626/7 devices) of on-chip RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction ...
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C8051T620/1/6/7 & C8051T320/1/2/3 equal to twice the SYSCLK (USBCLK > SYSCLK). When this bit is set, the USB FIFO space is mapped into XRAM space at addresses 0x0400 to 0x07FF. The normal on-chip XRAM at the same addresses ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Same 8192 bytes as 0xFFFF 0x0000 to 0x1FFF, wrapped at 8192-byte 0x2000 0x1FFF USB FIFO space repeated 3 times 0x1400 0x13FF 0x13C0 0x13BF 0x1340 0x133F 0x1240 0x123F 0x1040 0x103F 0x1000 0x0FFF On-Chip XRAM (3kB) and 1kB empty ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 15.2. EMI0CF: External Memory Configuration Bit 7 6 USBFAE Name R R/W Type 0 0 Reset SFR Address = 0x85 Bit Name 7 Unused Read = 0b; Write = Don’t Care. 6 USBFAE USB FIFO ...
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C8051T620/1/6/7 & C8051T320/1/2/3 16. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051T620/1/6/7 & C8051T320/1/2/3's resources and peripherals. The CIP-51 controller ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 Accumulator ACC 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH 0xC3 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xF5 In-Application Programming Control IAPCN 0xA8 Interrupt Enable IE 0xB8 Interrupt Priority IP 0xE4 INT0/INT1 Configuration IT01CF ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xFC PCA Capture 0 High PCA0CPH0 0xEA PCA Capture 1 High PCA0CPH1 0xEC PCA Capture 2 High ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xB4 UART1 Baud Rate Generator Low Byte SBRLL1 0x99 UART0 Data Buffer SBUF0 0xD3 UART1 Data Buffer ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 16.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0x95 Timer/Counter 3 High TMR3H 0x94 Timer/Counter 3Low TMR3L 0x93 Timer/Counter 3 Reload High TMR3RLH 0x92 Timer/Counter ...
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C8051T620/1/6/7 & C8051T320/1/2/3 17. Interrupts The C8051T620/1/6/7 & C8051T320/1/2/3 include an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripher- als and external inputs pins varies according ...
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C8051T620/1/6/7 & C8051T320/1/2/3 17.1. MCU Interrupt Sources and Vectors The C8051T620/1/6/7 & C8051T320/1/2/3 MCUs support 18 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 17.1. Interrupt Summary Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = Don't Care. 6 PSPI0 Serial Peripheral ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 PCP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This bit sets the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name Type R/W R/W Reset 0 0 SFR Address = 0xE7 Bit Name 7:3 Unused Read = 0000b, Write = Don't Care. 4 Reserved Must write ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xF7 Bit Name 7:5 Unused Read = 0000b, Write = Don't Care. 4 Reserved Must Write ...
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C8051T620/1/6/7 & C8051T320/1/2/3 17.3. INT0 and INT1 External Interrupt Sources The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 17.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is ...
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C8051T620/1/6/7 & C8051T320/1/2/3 18. Program Memory (EPROM) C8051T620/1/6/7 & C8051T320/1/2/3 devices include 64, 32 on-chip byte-programmable EPROM for program code storage. The EPROM memory can be programmed via the C2 debug and pro- gramming interface when ...
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C8051T620/1/6/7 & C8051T320/1/2/3 18.1.2. EPROM In-Application Programming The EPROM of the C8051T620/1/6/7 & C8051T320/1/2/3 devices has an In-Application Programming option. In-Application Programming will be much slower than normal programming where the V gramming voltage is applied to the V where ...
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C8051T620/1/6/7 & C8051T320/1/2/3 18.2. Security Options The C8051T620/1/6/7 & C8051T320/1/2/3 devices provide security options to prevent unauthorized view- ing of proprietary program code and constants. A security byte stored in the EPROM address space can be used to lock the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector, for example, ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 18.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x8F Bit Name 7:1 Unused Read = 0000000b. Write = don’t care. 0 PSWE Program Store ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 18.3. IAPCN: In-Application Programming Control Bit 7 6 IAPEN IAPDISD Name R/W R/W Type 0 0 Reset SFR Address = 0xF5 Bit Name 7 IAPEN In-Application Programming Enable. 0: In-Application Programming is disabled. 1: In-Application ...
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C8051T620/1/6/7 & C8051T320/1/2/3 19. Power Management Modes The C8051T620/1/6/7 & C8051T320/1/2/3 devices have three software programmable power manage- ment modes: Idle, Stop, and Suspend. Idle mode and stop mode are part of the standard 8051 architec- ture, while suspend mode ...
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C8051T620/1/6/7 & C8051T320/1/2/3 vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi- nitely, waiting for an external stimulus to wake up the system. Refer to Section “20.6. PCA Watchdog Timer Reset” on ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 19.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 20. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are ...
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C8051T620/1/6/7 & C8051T320/1/2/3 20.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases ...
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C8051T620/1/6/7 & C8051T320/1/2/3 the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 20.1. VDM0CN: V Bit 7 6 VDMEN VDDSTAT Name R/W R Type Varies Varies Reset SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until ...
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C8051T620/1/6/7 & C8051T320/1/2/3 20.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 20.2. RSTSRC: Reset Source Bit 7 6 USBRSF MEMERR C0RSEF Name R/W R Type Varies Varies Reset SFR Address = 0xEF Bit Name Description 7 USBRSF USB Reset Flag 6 MEMERR EPROM Error Reset Flag. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21. Oscillators and Clock Selection C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high- frequency oscillator can be enabled/disabled and calibrated using ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.1. System Clock Selection The CLKSL[2:0] bits in register CLKSEL select which oscillator source is used as the system clock. CLKSL[2:0] must be set to 001b for the system clock to run from the external oscillator; however ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.1. CLKSEL: Clock Select Bit 7 6 USBCLK[2:0] Name R Type 0 0 Reset SFR Address = 0xA9 Bit Name 7 Unused Read = 0b; Write = Don’t Care 6:4 USBCLK[2:0] USB Clock Source Select ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.3. Programmable Internal High-Frequency (H-F) Oscillator All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscilla- tor that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.4. Clock Multiplier The C8051T620/1/6/7 & C8051T320/1/2/3 device includes a 48 MHz high-frequency oscillator instead MHz oscillator and a 4x Clock Multiplier, so the USB0 module can be run directly from the internal high- ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.5. Programmable Internal Low-Frequency (L-F) Oscillator All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable low-frequency internal oscilla- tor, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.6. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. Figure 21.1 shows a block diagram of the ...
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C8051T620/1/6/7 & C8051T320/1/2 kHz 13 pF Figure 21.2. External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL ...
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C8051T620/1/6/7 & C8051T320/1/2/3 21.6.2. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 21.1, “RC Mode”. The capacitor should be no greater than ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 21.6. OSCXCN: External Oscillator Control Bit 7 6 Name XCLKVLD XOSCMD[2:0] R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status and is valid ...
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C8051T620/1/6/7 & C8051T320/1/2/3 22. Port Input/Output Digital and analog resources are available through 21, 24 I/O pins, depending on the specific device. Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal ...
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C8051T620/1/6/7 & C8051T320/1/2/3 22.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On ...
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C8051T620/1/6/7 & C8051T320/1/2/3 22.1.3. Interfacing Port I Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than V and less than 5.25V. An external ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 22.2. Port I/O Assignment for Digital Functions Digital Function UART0, SPI0, SMBus, CP0, Any Port pin available for assignment by the CP0A, CP1, CP1A, Crossbar. This includes P0.0 - P2.6 pins which SYSCLK, PCA0 (CEX0-4 have ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 22.3. Port I/O Assignment for External Digital Event Capture Functions Digital Function External Interrupt 0 External Interrupt 1 Port Match 22.3. Priority Crossbar Decoder The Priority Crossbar Decoder assigns a priority to each I/O function, starting ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 ...
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... Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will deter- mine the Port I/O pin-assignments based on the XBRn Register settings. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 Name CP1AE CP1E CP0AE Type R/W R/W Reset 0 0 SFR Address = 0xE1 Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous CP1 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE Type R/W R/W Reset 0 0 SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2 Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xE3 Bit Name 7:2 Unused Read = 0000000b; Write = Don’t Care. 1 Reserved Must ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.4. P0MASK: Port 0 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xAE Bit Name 7:0 P0MASK[7:0] Port 0 Mask Value. Selects P0 pins to be compared to the corresponding ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.6. P1MASK: Port 1 Mask Register Bit 7 6 Name Type Reset 0 0 SFR Address = 0xBA Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the corresponding ...
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C8051T620/1/6/7 & C8051T320/1/2/3 22.6. Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.9. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.11. P0SKIP: Port 0 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.13. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.15. P1SKIP: Port 1 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD5 Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.17. P2MDIN: Port 2 Input Mode Bit 7 6 Name Type Reset 1 1 SFR Address = 0xF3 Bit Name 7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively). Port pins configured for analog mode have ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.19. P2SKIP: Port 2 Skip Bit 7 6 Name Type Reset 0 0 SFR Address = 0xD6 Bit Name 7:0 P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to be ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 22.21. P3MDOUT: Port 3 Output Mode Bit 7 6 Name Type R R Reset 0 0 SFR Address = 0xA7 Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care 0 P3MDOUT[0] Output Configuration ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23. Universal Serial Bus Controller (USB0) C8051T620/1/6/7 & C8051T320/1/2/3 devices include a complete Full/Low Speed USB function for USB peripheral implementations. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi- directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 23.1. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 23.1. USB0XCN: USB0 Transceiver Control Bit 7 6 PREN PHYEN SPEED Name R/W R/W Type 0 0 Reset SFR Address = 0xD7 Bit Name 7 PREN Internal Pull-up Resistor Enable. The location of the pull-up ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.3. USB Register Access The USB0 controller registers listed in Table 23.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 23.2. USB0ADR: USB0 Indirect Address Bit 7 6 BUSY AUTORD Name R/W R/W Type 0 0 Reset SFR Address = 0x96 Bit Name Description 7 BUSY USB0 Register Read Busy Flag. This bit is used ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 23.3. USB0DAT: USB0 Data Bit 7 6 Name Type 0 0 Reset SFR Address = 0x97 Bit Name Description 7:0 USB0DAT[7:0] USB0 Data Bits. This SFR is used to indi- rectly read and write USB0 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 23.2. USB0 Controller Registers USB Register USB Register Name Address IN1INT 0x02 OUT1INT 0x04 CMINT 0x06 IN1IE 0x07 OUT1IE 0x09 CMIE 0x0B FADDR 0x00 POWER 0x01 FRAMEL 0x0C FRAMEH 0x0D INDEX 0x0E CLKREC 0x0F EENABLE 0x1E ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.4. INDEX: USB0 Endpoint Index Bit 7 6 Name Type R R Reset 0 0 USB Register Address = 0x0E Bit Name 7:4 Unused Read = 0000b. Write = don’t care. 3:0 EPSEL[3:0] Endpoint ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.5. FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 23.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, ...
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C8051T620/1/6/7 & C8051T320/1/2/3 0x13FF Endpoint0 (64 bytes) 0x13C0 0x13BF Endpoint1 (128 bytes) 0x1340 0x133F Endpoint2 (256 bytes) 0x1240 0x123F Endpoint3 (512 bytes) 0x1040 0x103F (64 bytes) 0x1000 0x0FFF User XRAM (3072 bytes, followed by 1024 bytes unused space) 0x0000 Figure ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 23.3. FIFO Configurations Endpoint Split Mode Number Enabled 23.5.1. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.6. Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7- bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.7. Function Configuration and Control The USB register POWER (USB Register Definition 23.8) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.8. POWER: USB0 Power Bit 7 6 ISOUD Name R/W R/W Type 0 0 Reset USB Register Address = 0x01 Bit Name 7 ISOUD ISO Update Bit. This bit affects all IN Isochronous endpoints. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.9. FRAMEL: USB0 Frame Number Low Bit 7 6 Name Type 0 0 Reset USB Register Address = 0x0C Bit Name 7:0 FRMEL[7:0] Frame Number Low Bits. This register contains bits 7-0 of the ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.8. Interrupts The read-only USB0 interrupt flags are located in the USB registers shown in USB Register Definition 23.11 through USB Register Definition 23.13. The associated interrupt enable bits are located in the USB registers shown in ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.12. OUT1INT: USB0 OUT Endpoint Interrupt Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x04 Bit Name 7:4 Unused Read = 0000b. Write = don’t care. 3 OUT3 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.13. CMINT: USB0 Common Interrupt Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x06 Bit Name 7:4 Unused Read = 0000b. Write = don’t care. 3 SOF Start ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.14. IN1IE: USB0 IN Endpoint Interrupt Enable Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x07 Bit Name 7:4 Unused Read = 0000b. Write = don’t care. 3 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x09 Bit Name 7:4 Unused Read = 0000b. Write = don’t care. 3 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.16. CMIE: USB0 Common Interrupt Enable Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x0B Bit Name 7:4 Unused Read = 0000b. Write = don’t care. 3 SOFE ...
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C8051T620/1/6/7 & C8051T320/1/2/3 5. Hardware sets the SUEND bit (E0CSR.4) because a control transfer ended before firmware sets the DATAEND bit (E0CSR.3). The E0CNT register (USB Register Definition 23.11) holds the number of received data bytes in the Endpoint0 FIFO. ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.10.3. Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.17. E0CSR: USB0 Endpoint0 Control Bit 7 6 SSUEND SOPRDY Name R/W R/W Type 0 0 Reset USB Register Address = 0x11 Bit Name Description 7 SSUEND Serviced Setup End Bit. 6 SOPRDY Serviced ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.18. E0CNT: USB0 Endpoint0 Data Count Bit 7 6 Name R Type 0 0 Reset USB Register Address = 0x16 Bit Name 7 Unused Read = 0b. Write = don’t care. 6:0 E0CNT[6:0] Endpoint ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.19. EENABLE: USB0 Endpoint Enable Bit 7 6 Name R R Type 1 1 Reset USB Register Address = 0x1E Bit Name 7:4 Unused Read = 1111b. Write = don’t care. 3 EEN3 Endpoint ...
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C8051T620/1/6/7 & C8051T320/1/2/3 ates a STALL condition, an interrupt will be generated and the STSTL bit (EINCSRL.5) set to 1. The STSTL bit must be reset firmware. Hardware will automatically reset INPRDY to 0 when a packet ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.20. EINCSRL: USB0 IN Endpoint Control Low Bit 7 6 CLRDT Name R W Type 0 0 Reset USB Register Address = 0x11 Bit Name Description 7 Unused Read = 0b. Write = don’t ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.21. EINCSRH: USB0 IN Endpoint Control High Bit 7 6 DBIEN ISO DIRSEL Name R/W R/W Type 0 0 Reset USB Register Address = 0x12 Bit Name 7 DBIEN IN Endpoint Double-buffer Enable. 0: ...
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C8051T620/1/6/7 & C8051T320/1/2/3 23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode When the ISO bit (EOUTCSRH. the target endpoint operates in Bulk or Interrupt mode. Once an end- point has been configured to operate in Bulk/Interrupt OUT mode (typically ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte Bit 7 6 CLRDT STSTL SDSTL Name W R/W Type 0 0 Reset USB Register Address = 0x14 Bit Name Description 7 CLRDT Clear Data Toggle ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte Bit 7 6 DBOEN ISO Name R/W R/W Type 0 0 Reset USB Register Address = 0x15 Bit Name 7 DBOEN Double-buffer Enable. 0: Double-buffering disabled ...
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C8051T620/1/6/7 & C8051T320/1/2/3 USB Register Definition 23.25. EOUTCNTH: USB0 OUT Endpoint Count High Bit 7 6 Name R R Type 0 0 Reset USB Register Address = 0x17 Bit Name 7:2 Unused Read = 000000b. Write = don’t care. 1:0 ...
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C8051T620/1/6/7 & C8051T320/1/2/3 24. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte ...
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C8051T620/1/6/7 & C8051T320/1/2/3 24.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I ...
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C8051T620/1/6/7 & C8051T320/1/2/3 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is ...
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C8051T620/1/6/7 & C8051T320/1/2/3 overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 24.3.5. SCL High (SMBus Free) Timeout ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Table 24.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When ...
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C8051T620/1/6/7 & C8051T320/1/2/3 Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA ...
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C8051T620/1/6/7 & C8051T320/1/2/3 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to ...