C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 76

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

C8051T620/1/6/7 & C8051T320/1/2/3
13. Prefetch Engine
The C8051T620/1/6/7 & C8051T320/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because
the access time of the EPROM memory is 40 ns, and the minimum instruction time is roughly 20 ns, the
prefetch engine is necessary for full-speed code execution. Instructions are read from EPROM memory
two bytes at a time by the prefetch engine and given to the CIP-51 processor core to execute. When run-
ning linear code (code without any jumps or branches), the prefetch engine allows instructions to be exe-
cuted at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles
while the next set of code bytes is retrieved from EPROM memory.
Note: The prefetch engine should be disabled when the device is in suspend mode to save power.
SFR Definition 13.1. PFE0CN: Prefetch Engine Control
SFR Address = 0xAF
76
Name
Reset
7:6
4:0
Bit
Type
5
Bit
Unused
Unused
Name
PFEN
R
7
0
Read = 00b, Write = don’t care.
Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Read = 00000b. Write = don’t care.
R
6
0
PFEN
R/W
5
1
Rev. 1.2
R
4
0
Function
R
3
0
R
2
0
R
1
0
R
0
0