C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 129

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

SFR Definition 21.1. CLKSEL: Clock Select
SFR Address = 0xA9
Name
Reset
6:4 USBCLK[2:0] USB Clock Source Select Bits.
2:0
Bit
Type
7
3
Bit
CLKSL[2:0]
OUTCLK
Unused
Name
R
7
0
Read = 0b; Write = Don’t Care
000: USBCLK derived from the Internal High-Frequency Oscillator.
001: USBCLK derived from the Internal High-Frequency Oscillator / 8.
010: USBCLK derived from the External Oscillator.
011: USBCLK derived from the External Oscillator / 2.
100: USBCLK derived from the External Oscillator / 3.
101: USBCLK derived from the External Oscillator / 4.
110: USBCLK derived from the Internal Low-Frequency Oscillator.
111: RESERVED.
Crossbar Clock Out Select.
If the SYSCLK signal is enabled on the Crossbar, this bit selects between outputting
SYSCLK and SYSCLK synchronized with the Port I/O pins.
0: Enabling the Crossbar SYSCLK signal outputs SYSCLK.
1: Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the
Port I/O.
System Clock Source Select Bits.
000: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per
the IFCN bits in register OSCICN.
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the Internal High-Frequency Oscillator / 2.
011: SYSCLK derived from the Internal High-Frequency Oscillator.
100: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per
the OSCLD bits in register OSCLCN.
101-111: RESERVED.
6
0
C8051T620/1/6/7 & C8051T320/1/2/3
USBCLK[2:0]
R/W
5
0
Rev. 1.2
4
0
OUTCLK
Function
R/W
3
0
2
0
CLKSL[2:0]
R/W
1
0
0
0
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