C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 145

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C8051T627-B-GM

Manufacturer Part Number
C8051T627-B-GM
Description
8-bit Microcontrollers - MCU UBS, 64K OTP MCU
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051T627-B-GM

Rohs
yes
Core
8051
Processor Series
C8051T627
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Program Memory Size
64 KB
Data Ram Size
3328 B
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 5.25 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-32
Mounting Style
SMD/SMT
Program Memory Type
EPROM
In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SPI
signals, and three PCA signals. Note that the SPI signals are assigned as multiple signals.
Additionally, pins P0.0, P0.2, and P0.3 are configured to be skipped using the P0SKIP register.
1
2
3
4
All unassigned pins, including those skipped by XBR0 can be used as GPIO or for other non-
crossbar functions.
Notes:
1. P2.4-P2.7 are only available in certain packages.
Pin Number
st
nd
rd
th
TX0 is assigned to P0.4
SYSCLK
SCK, MISO, MOSI, and NSS are assigned to P0.1, P0.6, P0.7, and P1.0, respectively.
CEX0, CEX1, and CEX2 are assigned to P1.1, P1.2, and P1.3, respectively.
Function
RX0 is assigned to P0.5
These boxes represent the port pins which are used by the peripherals in this configuration.
Pin Skip
Settings
Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins
Special
Signals
CP0A
CP1A
CEX0
CEX1
CEX2
CEX3
CEX4
MISO
MOSI
SCK
NSS
SDA
RX0
SCL
CP0
CP1
RX1
Port
TX0
TX1
ECI
T0
T1
0
1 0 1 1 0 0 0 0
1 2 3 4 5 6 7 0
C8051T620/1/6/7 & C8051T320/1/2/3
P0SKIP
P0
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7
Rev. 1.2
P1SKIP
P1
0
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7
P2SKIP
P2
1
0
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