C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 122

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

C8051T620/1/6/7 & C8051T320/1/2/3
20.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on or V
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V
is enabled following a power-on reset.
20.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 20.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
122
Logic HIGH
RST
Logic LOW
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
ramp time is defined as how fast V
DD
RST
RST
monitor event timing. The maximum V
, the CIP-51 will be released from the reset state. Note that even though internal data
Figure 20.2. Power-On and V
V
RST
DD
Power-On
monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
DD
PORDelay
Reset
Monitor
T
) is typically less than 0.3 ms.
PORDelay
Rev. 1.2
DD
DD
DD
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
DD
to drop below V
RST
Monitor
Reset
VDD
level. For ramp times less than
RST
). Figure 20.2. plots the
RST
, the power supply
DD
DD
dropped below
settles above
DD
VDD
DD
ramp time
DD
monitor
returns
t