C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 114

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

C8051T620/1/6/7 & C8051T320/1/2/3
18.2. Security Options
The C8051T620/1/6/7 & C8051T320/1/2/3 devices provide security options to prevent unauthorized view-
ing of proprietary program code and constants. A security byte stored in the EPROM address space can
be used to lock the program memory from being read or written across the C2 interface. On the
C8051T626/7 devices, the security byte is located at address 0xFFF8. On the C8051T620/1 and
C8051T320/1/2/3, the security byte is located at address 0x3FF8. The lock byte can always be read
regardless of the security settings. Table 18.1 shows the security byte decoding. Refer to
“Figure 15.3. Program Memory Map” on page 89 for the location of the security byte in EPROM memory.
Important Note: Once the security byte has been written, there are no means of unlocking the device.
Locking memory from write access should be performed only after all other code has been successfully
programmed to memory.
18.3. EPROM Writing Guidelines
Any system which contains routines which write EPROM memory from software involves some risk that
the write routines will execute unintentionally if the CPU is operating outside its specified operating range
of V
result in alteration of EPROM memory contents causing a system failure.
The following guidelines are recommended for any system which contains routines which write EPROM
memory from code.
18.3.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. Make certain that the minimum V
3. Enable the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
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devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
this rise time specification, then add an external V
holds the device in reset until V
possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based
systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
Monitor reset source must be enabled to write the EPROM without generating an EPROM Error Device
Reset.
source inside the functions that write EPROM memory. The V
placed just after the instruction to set PSWE to a 1, but before the EPROM write operation instruction.
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example,"RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
DD
DD
, system clock frequency, or temperature. This accidental execution of EPROM modifying code can
monitor and enabling the V
Bits
7–4
3–0
DD
monitor and enable the V
Write Lock: Clearing any of these bits to logic 0 prevents all code
memory from being written across the C2 interface.
Read Lock: Clearing any of these bits to logic 0 prevents all code
memory from being read across the C2 interface.
Table 18.1. Security Byte Decoding
DD
DD
DD
monitor as a reset source. Note: Both the VDD Monitor and the VDD
reaches V
rise time specification of 1 ms is met. If the system cannot meet
RST
Rev. 1.2
DD
and re-asserts RST if V
DD
DD
monitor and enable the V
monitor as a reset source as early in code as
brownout circuit to the RST pin of the device that
Description
DD
monitor enable instructions should be
DD
DD
drops below V
monitor as a reset
RST
.