C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 91

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

15.2.2. External RAM
There are 1024 bytes (C8051T620/1/320/1/2/3 devices) or 3072 bytes (C8051T626/7 devices) of on-chip
RAM mapped into the external data memory space. All of these address locations may be accessed using
the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing
mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of
the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in
SFR Definition 15.1).
For a 16-bit MOVX operation (@DPTR), the upper three or five bits of the 16-bit external data memory
address word are "don't cares" (when USBFAE is cleared to 0). As a result, the XRAM is mapped modulo
style over the entire 64 k external data memory address range. For example, on the C8051T620/1 the
XRAM byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0C00, 0x1000, etc. This is a
useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when
reaching the RAM block boundary.
SFR Definition 15.1. EMI0CN: External Memory Interface Control
SFR Address = 0xAA
15.2.3. Accessing USB FIFO Space
The C8051T620/1/6/7 & C8051T320/1/2/3 include 1k of RAM which functions as USB FIFO space.
Figure 15.4 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally
accessed via USB FIFO registers; see Section “23.5. FIFO Management” on page 169 for more informa-
tion on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in
the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to 1, and (2) the USB clock frequency must be greater than or
Name
Reset
Bit
7:5
4:0 PGSEL[4:0] XRAM Page Select.
Type
Bit
Unused
Name
R
7
0
Read = 00000b; Write = Don’t Care.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL
determines which page of XRAM is accessed.
For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be
accessed.
Note: PGSEL[4:3] are only valid on the C8051T626/7 devices.
R
6
0
C8051T620/1/6/7 & C8051T320/1/2/3
R
5
0
R/W
Rev. 1.2
4
0
Function
R/W
3
0
PGSEL[4:0]
R/W
2
0
R/W
1
0
R/W
0
0
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