C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 6

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

C8051T620/1/6/7 & C8051T320/1/2/3
25. UART0 ................................................................................................................... 215
26. UART1 ................................................................................................................... 223
27. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 233
6
24.4. Using the SMBus........................................................................................... 197
24.5. SMBus Transfer Modes................................................................................. 207
24.6. SMBus Status Decoding................................................................................ 210
25.1. Enhanced Baud Rate Generation.................................................................. 216
25.2. Operational Modes ........................................................................................ 217
25.3. Multiprocessor Communications ................................................................... 219
26.1. Baud Rate Generator .................................................................................... 223
26.2. Data Format................................................................................................... 225
26.3. Configuration and Operation ......................................................................... 226
27.1. Signal Descriptions........................................................................................ 234
27.2. SPI0 Master Mode Operation ........................................................................ 235
27.3. SPI0 Slave Mode Operation .......................................................................... 236
27.4. SPI0 Interrupt Sources .................................................................................. 237
27.5. Serial Clock Phase and Polarity .................................................................... 237
27.6. SPI Special Function Registers ..................................................................... 239
24.3.1. Transmitter Vs. Receiver....................................................................... 196
24.3.2. Arbitration.............................................................................................. 196
24.3.3. Clock Low Extension............................................................................. 196
24.3.4. SCL Low Timeout.................................................................................. 196
24.3.5. SCL High (SMBus Free) Timeout ......................................................... 197
24.4.1. SMBus Configuration Register.............................................................. 197
24.4.2. SMB0CN Control Register .................................................................... 201
24.4.3. Hardware Slave Address Recognition .................................................. 203
24.4.4. Data Register ........................................................................................ 206
24.5.1. Write Sequence (Master) ...................................................................... 207
24.5.2. Read Sequence (Master) ...................................................................... 208
24.5.3. Write Sequence (Slave) ........................................................................ 209
24.5.4. Read Sequence (Slave) ........................................................................ 210
25.2.1. 8-Bit UART ............................................................................................ 217
25.2.2. 9-Bit UART ............................................................................................ 218
26.3.1. Data Transmission ................................................................................ 226
26.3.2. Data Reception ..................................................................................... 226
26.3.3. Multiprocessor Communications ........................................................... 227
27.1.1. Master Out, Slave In (MOSI)................................................................. 234
27.1.2. Master In, Slave Out (MISO)................................................................. 234
27.1.3. Serial Clock (SCK) ................................................................................ 234
27.1.4. Slave Select (NSS) ............................................................................... 234
24.4.2.1. Software ACK Generation ............................................................ 201
24.4.2.2. Hardware ACK Generation ........................................................... 201
Rev. 1.2