C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 138

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

C8051T620/1/6/7 & C8051T320/1/2/3
22. Port Input/Output
Digital and analog resources are available through 21, 24, or 25 I/O pins, depending on the specific device.
Port pins P0.0-P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 22.3. Port pin P3.0 on can be used as
GPIO and is shared with the C2 Interface Data signal (C2D). The designer has complete control over
which functions are assigned, limited only by the number of physical I/O pins. This resource assignment
flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin
can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 22.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 22.1, SFR Definition 22.2,
and SFR Definition 22.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 7.3 on page 36.
138
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
Outputs
UART0
SMBus
UART1
T0, T1
P0
P1
P2
P3
PCA
CP0
CP1
SPI
Figure 22.1. Port I/O Functional Block Diagram
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.6)
(P3.0)
2
4
2
2
2
6
2
2
8
8
7
1
Rev. 1.2
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Registers
Priority
Digital
(ADC0, CP0, CP1, VREF,
To Analog Peripherals
EXTCLK)
8
8
7
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cells
Cell
I/O
I/O
I/O
I/O
P0
P1
P2
P3
PnMDIN Registers
External Interrupts
EX0 and EX1
PnMDOUT,
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0