C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 176
C8051T627-B-GM
Manufacturer Part Number
C8051T627-B-GM
Description
8-bit Microcontrollers - MCU UBS, 64K OTP MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051T626-B-GM.pdf
(298 pages)
Specifications of C8051T627-B-GM
Rohs
yes
Core
8051
Processor Series
C8051T627
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Program Memory Size
64 KB
Data Ram Size
3328 B
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 5.25 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-32
Mounting Style
SMD/SMT
Program Memory Type
EPROM
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C8051T620/1/6/7 & C8051T320/1/2/3
23.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 23.11 through USB Register Definition 23.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 23.14 through USB Register Definition 23.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to 1. The USB0 interrupt is enabled via the
EIE1 SFR (see Section “17. Interrupts” on page 101).
Important Note: Reading a USB interrupt flag register resets all flags in that register to 0.
USB Register Definition 23.11. IN1INT: USB0 IN Endpoint Interrupt
USB Register Address = 0x02
176
Name
Reset
7:4
Bit
Type
3
2
1
0
Bit
Unused
Name
EP0
IN3
IN2
IN1
R
7
0
Read = 0000b. Write = don’t care.
IN Endpoint 3 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 3 interrupt inactive.
1: IN Endpoint 3 interrupt active.
IN Endpoint 2 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 2 interrupt inactive.
1: IN Endpoint 2 interrupt active.
IN Endpoint 1 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: IN Endpoint 1 interrupt inactive.
1: IN Endpoint 1 interrupt active.
Endpoint 0 Interrupt-Pending Flag.
This bit is cleared when software reads the IN1INT register.
0: Endpoint 0 interrupt inactive.
1: Endpoint 0 interrupt active.
R
6
0
R
5
0
Rev. 1.2
R
4
0
Function
IN3
R
3
0
IN2
R
2
0
IN1
R
1
0
EP0
R
0
0
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