C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 8

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

C8051T620/1/6/7 & C8051T320/1/2/3
List of Figures
8
Figure 1.1. C8051T620/1 Block Diagram ................................................................ 16
Figure 1.2. C8051T626/7 Block Diagram ................................................................ 17
Figure 1.3. C8051T320/2 Block Diagram ................................................................ 18
Figure 1.4. C8051T321/3 Block Diagram ................................................................ 19
Figure 1.5. Typical Bus-Powered Connections ....................................................... 20
Figure 3.1. QFN-32 Pinout Diagram (Top View) ..................................................... 25
Figure 3.2. LQFP-32 Pinout Diagram (Top View) .................................................... 26
Figure 3.3. QFN-28 Pinout Diagram (Top View) ..................................................... 27
Figure 4.1. LQFP-32 Package Drawing ................................................................... 28
Figure 4.2. LQFP-32 Recommended PCB Land Pattern ........................................ 29
Figure 5.1. QFN-32 Package Drawing .................................................................... 30
Figure 5.2. QFN-32 Recommended PCB Land Pattern .......................................... 31
Figure 6.1. QFN-28 Package Drawing .................................................................... 32
Figure 6.2. QFN-28 Recommended PCB Land Pattern .......................................... 33
Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) ......... 44
Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) ............... 44
Figure 8.1. ADC0 Functional Block Diagram ........................................................... 45
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing ............................. 47
Figure 8.3. ADC0 Equivalent Input Circuits ............................................................. 48
Figure 8.4. ADC Window Compare Example: Right-Justified Data ......................... 54
Figure 8.5. ADC Window Compare Example: Left-Justified Data ........................... 54
Figure 8.6. ADC0 Multiplexer Block Diagram .......................................................... 55
Figure 9.1. Temperature Sensor Transfer Function ................................................ 57
Figure 9.2. TOFFH and TOFFL Calibration Value Orientation ................................ 58
Figure 9.3. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ........... 58
Figure 10.1. Voltage Reference Functional Block Diagram ..................................... 59
Figure 11.1. REG0 Configuration: USB Bus-Powered ............................................ 61
Figure 11.2. REG0 Configuration: USB Self-Powered ............................................ 62
Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled ............ 62
Figure 11.4. REG0 Configuration: No USB Connection .......................................... 63
Figure 12.1. CIP-51 Block Diagram ......................................................................... 66
Figure 14.1. Comparator0 Functional Block Diagram ............................................. 77
Figure 14.2. Comparator1 Functional Block Diagram ............................................. 78
Figure 14.3. Comparator Hysteresis Plot ................................................................ 79
Figure 14.4. Comparator Input Multiplexer Block Diagram ...................................... 84
Figure 15.1. C8051T620/1 and C8051T320/1/2/3 Memory Map ............................. 87
Figure 15.2. C8051T626/7 Memory Map ................................................................. 88
Figure 15.3. Program Memory Map ......................................................................... 89
Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and 
Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map 
Figure 20.1. Reset Sources ................................................................................... 121
XRAM Memory Map with USBFAE Set to 1 ....................................................... 92
with USBFAE set to 1 ......................................................................................... 93
Rev. 1.2