C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 181

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

USB Register Definition 23.16. CMIE: USB0 Common Interrupt Enable
USB Register Address = 0x0B
23.9. The Serial Interface Engine
The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor
when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the
processor when a complete data packet has been received; appropriate handshaking signals are automat-
ically generated by the SIE. When transmitting data, the SIE will interrupt the processor when a complete
data packet has been transmitted and the appropriate handshake signal has been received.
The SIE will not interrupt the processor when corrupted/erroneous packets are received.
23.10. Endpoint0
Endpoint0 is managed through the USB register E0CSR (USB Register Definition 23.18). The INDEX reg-
ister must be loaded with 0x00 to access the E0CSR register.
An Endpoint0 interrupt is generated when:
1. A data packet (OUT or SETUP) has been received and loaded into the Endpoint0 FIFO. The OPRDY
2. An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the
3. An IN transaction is completed (this interrupt generated during the status stage of the transaction).
4. Hardware sets the STSTL bit (E0CSR.2) after a control transaction ended due to a protocol violation.
Name
Reset
Bit
7:4
Type
3
2
1
0
Bit
bit (E0CSR.0) is set to 1 by hardware.
host; INPRDY is reset to 0 by hardware.
RSUINTE
SUSINTE
RSTINTE
Unused
Name
SOFE
R
7
0
Read = 0000b. Write = don’t care.
Start of Frame Interrupt Enable.
0: SOF interrupt disabled.
1: SOF interrupt enabled.
Reset Interrupt Enable.
0: Reset interrupt disabled.
1: Reset interrupt enabled.
Resume Interrupt Enable.
0: Resume interrupt disabled.
1: Resume interrupt enabled.
Suspend Interrupt Enable.
0: Suspend interrupt disabled.
1: Suspend interrupt enabled.
R
6
0
C8051T620/1/6/7 & C8051T320/1/2/3
R
5
0
Rev. 1.2
R
4
0
Function
SOFE
R/W
3
0
RSTINTE
R/W
2
1
RSUINTE SUSINTE
R/W
1
1
R/W
0
0
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