C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 121

• Manufacturer Part Number: C8051T627-B-GM
• Description: 8-bit Microcontrollers - MCU UBS, 64K OTP MCU
• Manufacturer: Silicon Labs

Specifications of C8051T627-B-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051T627
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 3328 B
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-32
• Mounting Style: SMD/SMT
• Program Memory Type: EPROM

20. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:




All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
EXTCLK
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Frequency
Oscillator
Oscillator
Oscillator
External
Internal
Drive
Low
Px.x
Px.x
Clock Select
System
Clock
DD
C8051T620/1/6/7 & C8051T320/1/2/3
Comparator 0
Monitor and power-on resets, the RST pin is driven low until the device
+
-
Figure 20.1. Reset Sources
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Core
Handler
WDT
PCA
EN
Rev. 1.2
VDD
System Reset
Supply
Monitor
+
-
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
Errant OTP
Operation
(wired-OR)
Reset
Funnel
RST
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