C8051T627-B-GM Silicon Labs, C8051T627-B-GM Datasheet - Page 130
C8051T627-B-GM
Manufacturer Part Number
C8051T627-B-GM
Description
8-bit Microcontrollers - MCU UBS, 64K OTP MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051T626-B-GM.pdf
(298 pages)
Specifications of C8051T627-B-GM
Rohs
yes
Core
8051
Processor Series
C8051T627
Data Bus Width
8 bit
Maximum Clock Frequency
48 MHz
Program Memory Size
64 KB
Data Ram Size
3328 B
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 5.25 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-32
Mounting Style
SMD/SMT
Program Memory Type
EPROM
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C8051T620/1/6/7 & C8051T320/1/2/3
21.3. Programmable Internal High-Frequency (H-F) Oscillator
All C8051T620/1/6/7 & C8051T320/1/2/3 devices include a programmable internal high-frequency oscilla-
tor that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via
the OSCICL register as defined by SFR Definition 21.2.
On C8051T620/1/6/7 & C8051T320/1/2/3 devices, OSCICL is factory calibrated to obtain a 48 MHz base
frequency. Note that the system clock may be derived from the programmed internal oscillator divided by
1, 2, 4, or 8 after a divide by 4 stage, as defined by the IFCN bits in register OSCICN. The divide value
defaults to 8 following a reset, which results in a 1.5 MHz system clock.
21.3.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to the SUSPEND bit.
Note: The prefetch engine can be turned off in suspend mode to save power. Additionally, both Voltage
Regulators (REG0 and REG1) have low-power modes for additional power savings in suspend mode. See
Section “13. Prefetch Engine” on page 76 and Section “11. Voltage Regulators (REG0 and REG1)” on
page 61 for more information.
SFR Definition 21.2. OSCICL: Internal H-F Oscillator Calibration
SFR Address = 0xB3
130
Name
Reset
6:0 OSCICL[6:0] Internal Oscillator Calibration Bits.
Bit
Type
7
Bit
Port 0 Match Event.
Port 1 Match Event.
Timer3 Overflow Event.
USB0 Transceiver Resume Signalling
Unused
Name
R
7
0
Read = 0; Write = Don’t Care
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 48 MHz.
Varies
6
Varies
5
Varies
Rev. 1.2
4
OSCICL[6:0]
Function
Varies
R/W
3
Varies
2
Varies
1
Varies
0
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