PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 100

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-38. 32-bit Target Write Transaction with Master Wait State
Burst Read and Write Target Transactions
Burst read and write transactions to memory addresses are used to achieve the high throughput that is typically
associated with the PCI bus. The following lists the commands for the PCI IP core that support bursting.
• Memory Read
• Memory Write
• Memory Read Multiple
• Dual Address Cycle
• Memory Read Line
• Memory Write and Invalidate
These PCI burst transactions are described based on the different PCI and Local bus configurations supported by
the PCI IP core. Although the fundamentals of bursting are similar for all PCI IP core configurations, different bus
configurations require slightly different Local Target Interface signaling. The PCI IP core does not support bursting
for Configuration Space or I/O space accesses. Refer to the following sections for more information on bursting with
specific PCI Target configurations:
• 32-Bit PCI Target with a 32-Bit Local Bus
• 64-Bit PCI Target with a 64-Bit Local Bus
• 32-Bit PCI Target with a 64-Bit Local Bus
Typically for burst transactions, the PCI master and the PCI target has a predefined number of PCI data phases
that are to be transferred. The PCI master will know the number of data phases that are to be transferred based on
the software driver and specifications that were defined by the PCI IP core’s implementation. The PCI IP core will
have a predefined number of data phases based on the design requirements of the PCI Target core’s application.
The design requirements include items like FIFO depth and the general ability to handle throughput. Handling
these requirements is covered in more detail in the PCI Local Bus Specification, Revision 3.0.
CLK
10
1
2
3
4
5
6
7
8
9
Master Wait
Turn around
Target Wait The PCI master is ready to receive data. It asserts irdyn.
Target Wait The Core starts to decode the address and command.
Target Wait
PCI Data
Address
Phase
Data 1
Data 2
Data 3
Idle
The master asserts framen and drives ad[31:0] and cben[3:0].
If the DEVSEL_TIMING is set to slow, the target asserts devseln on clock after bar_hit.The
lt_rdyn signal is driven low to indicate that the back-end application is ready to receive data.
The irdyn and trdyn signals are asserted Data 1 is registered from ad[31:0].
With lt_data_xfern signal asserted Data1 is registered on lt_data_out[31:0].The master is not
ready to receive data. It inserts a wait state by de-asserting irdyn. The master holds Data 1 on
the ad[31:0] lines and continues to drive the first byte enables (Byte Enable 1).
With the irdyn signal asserted Data 2 is driven on to ad[31:0].Because irdyn is not asserted
on the previous cycle, the Core de-asserts lt_data_xfern on the local interface.
With the irdyn signal asserted Data 3 is driven on to ad[31:0].If both irdyn and lt_rdyn are
asserted on the previous cycle, the Core re-asserts lt_data_xfern to the back-end.
With lt_data_xfern signal asserted Data 2 is registered on lt_data_out[31:0].The master relin-
quishes control of framen, ad[31:0] and cben[3:0].The Core de-asserts both devseln and
trdyn if both trdyn and irdyn were asserted last cycle.
The Core relinquishes control of devseln and trdyn.
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Description
Functional Description
PCI IP Core User’s Guide