PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 141

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Interrupts
Interrupt Acknowledge
This option determines if the PCI core supports Interrupt Acknowledge.
Interrupt Pin
Indicates which Interrupt Pin will be used by the PCI Core.
PCI Master Tab (PCI Master/Target Cores Only)
Figure 3-4
Figure 3-4. PCI Master Tab
Read Only Latency Timer
A mechanism for ensuring that a bus master does not extend the access latency of other masters beyond a speci-
fied value.
MIN_GNT
An 8-bit parameter used to specify the length of time in microseconds for the Master to control the PCI bus.
MAX_LAT
An 8-bit parameter used to specify how often the PCI Core possess the bus.
BARs Tab
Figure 3-5
Figure 3-5. BARs Tab
shows the contents of the PCI Master tab. This example shows the PCI Master/Target 33.
shows the contents of the BARs tab. This example shows the PCI Master/Target 33.
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PCI IP Core User’s Guide
Parameter Settings