PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 80

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-27. Fast Back-to-Back Transaction (Continued)
CLK
13
14
15
16
17
18
Data 5 and 6
Data 7 and 8
Turn around
PCI Data
Phase
Wait
Wait
Idle
The Core de-asserts reqn when framen was asserted but lm_req64n was de-asserted on the
previous cycle.
If the target completes the fast decode and is ready to receive 64-bit data, it asserts devseln,
ack64n and trdyn.
With lm_ldata_xfern and lm_hdata_xfern asserted on the previous cycle that was the
address phase, the local master should increment the address counter while the Core transfers
Data 5 and Data 6 and their byte enables to ad[63:0] and cben[7:0].
With lm_rdyn asserted on the previous cycle, the local master provides Data 7 and Data 8 on
l_ad_in[63:0] and the byte enables on lm_cben_in[7:0].
Because this is the first write data phase and devseln is just asserted, the Core keeps framen
asserted and irdyn de-asserted to judge 64-bit or 32-bit transaction. It also de-asserts
lm_ldata_xfern and lm_hdata_xfern to the local master to signify Data 7 and Data 8 on
l_ad_in[63:0] are not read.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted.
Since irdyn is not asserted, the first data phase is not completed.
Since lm_ldata_xfern and lm_hdata_xfern were not asserted on the previous cycle, the
local master keeps Data 7 and Data 8 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0].
Because the Core needs one more cycle to decide 64-bit or 32-bit transaction, it keeps framen
asserted and irdyn de-asserted. It also keeps lm_ldata_xfern and lm_hdata_xfern de-
asserted to the local master to signify Data 7 and Data 8 on l_ad_in[63:0] are not read.
The Core asserts lm_64bit_transn to indicate the current data transaction is 64-bit wide. It de-
asserts lm_gntn to follow gntn.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted.
Since irdyn is not asserted, the first data phase is not completed.
Since lm_ldata_xfern and lm_hdata_xfern were not asserted on the previous cycle, the
local master keeps Data 7 and Data 8 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0].
With both devseln and lm_rdyn asserted previous cycle, the Core asserts irdyn, and it pre-
pares for the 64-bit write burst. So it asserts lm_ldata_xfern and lm_hdata_xfern to the
local master to signify Data 7 and Data 8 on l_ad_in[63:0] and the byte enables on
lm_cben_in[7:0] are being read and will be transferred to the PCI bus.
The Core keeps framen asserted and asserts irdyn. It also keeps lm_ldata_xfern and
lm_hdata_xfern de-asserted to the local master to signify Data 3 and Data 4 on
l_ad_in[63:0] are not read.
If the local master is ready to provide the next QWORD, it keeps lm_rdyn asserted.
Because the Core performs the burst transactions, it keeps framen asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’.
Since Data 5 and Data 6 on PCI bus were read, the Core transfers Data 7 and Data 8 and their
byte enables to ad[63:0] and [7:0].
With lm_rdyn asserted previous cycle, the Core keeps irdyn asserted.
Because the current transaction is the last, the Core de-asserts framen and req64n to signal the
end of the burst, also it de-asserts lm_ldata_xfern and lm_hdata_xfern.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
The Core relinquishes control of framen, req64n, ad and cben. It de-asserts irdyn, decreases
‘lm_burst_cnt’ to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle.The target de-asserts devseln, ack64n and trdyn.
The Core relinquishes control of irdyn, par and par64.
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Description
Functional Description
PCI IP Core User’s Guide