PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 99

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-37. 32-bit Target Read Transaction with Master Wait State (Continued)
Figure 2-33
tions. The figure illustrates how the PCI interface correlates to the Local Target Interface. The table gives a clock-
by-clock description of each event in the figure.
Figure 2-33. 32-bit Target Write Transaction with Master Wait State
CLK
10
11
8
9
l_data_out[31:0]
lt_address_out
lt_data_xfern
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
framen
lt_r_nw
lt_rdyn
and
irdyn
trdyn
Turn around
par
clk
PCI Data
Phase
Data 2
Data 3
Table 2-38
Idle
1
Don’t care
Command
Address
Bus
0x00
If the PCI master is ready to receive data, it asserts irdyn and drives the next byte enables (Byte
Enable 3) on cben[3:0].Because irdyn is not asserted on the previous cycle, the Core de-
asserts lt_data_xfern on the local interface.
Since the last data phase, the master asserts irdyn and de-asserts framen.If both irdyn and
lt_rdyn are asserted on the previous cycle, the Core re-asserts lt_data_xfern to the back-
end.
The master relinquishes control of framen, ad[31:0] and cben[3:0].The Core de-asserts
both devseln and trdyn.
The Core relinquishes control of devseln and trdyn.
2
show master-inserted and target-inserted wait states that are inserted on write transac-
Address
Parity
3
Don’t care
4
Byte Enable 1
Data 1
5
Data Parity 1
99
6
Address
0x01
Description
7
Data 1
Enable 2
Data 2
Byte
8
Data Parity
Enable 3
Data 3
Data 2
Byte
2
9
Functional Description
Data Parity 3
Data 3
PCI IP Core User’s Guide
10
Don’t care
0x00
11