PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 90

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-32. 64-bit Target Single Write Transaction with a 64-bit Local Interface
32-Bit PCI Target with a 64-Bit Local Bus
This section discusses read and write transactions for a PCI IP core, operating as a target, configured with a 32-bit
PCI bus and a 64-bit local bus. The 32-bit PCI transactions, described in the 32-Bit PCI Target with a 32-Bit Local
Bus Memory Transactions section, look similar to the transaction; however; the data is handled differently at the
Local Target Interface.
In order to present a full 64 bits of data to the Local Target Interface, two PCI data phase are required. Like retriev-
ing 64 bits of data from the Local Target Interface, two PCI data phases are required
The Local Target Interface control latches the complete QWORD and routes the proper DWORD to the PCI data
bus. The lt_ldata_xfern and lt_hdata_xfern signals specify which DWORD is transferred.
If the starting address is QWORD aligned, the first DWORD is assumed to be the lower DWORD of a QWORD and
is placed on the PCI data bus. Otherwise, the upper DWORD is placed on the PCI data bus.
The 64-bit memory write transaction is similar to the 32-bit target write transaction with additional PCI signals
required for 64-bit signaling.
CLK
1
2
3
4
5
6
7
8
Turn around
PCI Data
Address
Phase
Data 1
Wait
Wait
Wait
Idle
Idle
The master asserts framen and req64n and drives ad[63:0] and cben[3:0].
The master drives the first byte enables (Byte Enable 1). If the master is ready to write data, it
asserts irdyn and drives the first QWORD (Data 1) on ad[63:0].The Core starts to decode the
address and command. The Core drives the lt_address_out to the back-end. The
lt_64bit_transn signal is driven low to signal the back-end that a 64-bit transaction has been
requested.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use the bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on clock after bar_hit. The
ack64n signal is also asserted to acknowledge the 64-bit request. If the back-end will be ready to
put data out on the next cycle, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted during the previous cycle.
If both irdyn and trdyn are asserted during the previous cycle, the master relinquishes control
of framen, req64n, ad[63:0] and cben[7:0]. It also de-asserts irdyn if both trdyn and
irdyn were asserted last cycle.
The Core signals to the back-end that the transaction is complete by clearing bar_hit. It also de-
asserts lt_hdata_xfern and lt_ldata_xfern.
Figure 2-28
and
Table 2-33
90
illustrate a basic 64-bit write transaction.
Description
Functional Description
PCI IP Core User’s Guide