PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 31

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Basic PCI Master Read and Write Transactions
Read and write transactions to memory and I/O space are used to transfer data on the PCI bus. The basic read
and write transactions use the following PCI commands:
• I/O Read
• I/O Write
• Memory Read
• Memory Write
• Configuration Read
• Configuration Write
To simplify the integration of the PCI IP core, the basic master transactions are described based on different bus
con-figurations supported with this PCI IP core. Although the fundamentals of the basic master transactions are the
same, different bus configurations require slightly different local bus signaling. Refer to the following sections for
more information on the basic bus master transactions with specific PCI IP core configurations:
• 32-bit PCI Master with a 32-Bit Local Bus
• 64 bit PCI Master with a 64-Bit Local Bus
• 32-bit PCI Master with a 64-Bit Local Bus
Refer to the advanced bus master transactions in the Advanced Master Transactions section for more information
on properly handling wait state insertion and early termination of bus transactions by the PCI IP core.
Waveform Legend
32-bit PCI Master with a 32-bit Local Bus
This section discusses read and write transactions executed by the PCI IP core operating as a master, configured
with a 32-bit PCI bus and a 32-bit local bus. Because 32-bit I/O and memory transactions are alike, they are dis-
cussed together.
Figure 2-7
bit transaction shown in
Interface is important for a read transaction. The clock number in the waveforms is for the clock period, that is, after
the current rising clock edge.
Note: The clock number in the waveform is for the clock period, that is, after the current rising clock edge.
Don't care
Symbol
Data 4
illustrates a basic 32-bit read transaction.
Driven signal
Driven bus signals or driven PCI parity signal (par and par64).
Floated PCI signals. If the signal is high, it is high maintained by system pull-up resistor. If the signal is in
the middle of level place, it is tri-state.
Don’t care local signal. For input signal, the core doesn’t read it. For output signal, it is an invalid value.
1. Local interface: Don’t care bus signals. For input signals, the core doesn’t read it. For output signal,
they are invalid value. 2. PCI interface: the signal can be any value.
PCI signal turnaround. The core releases PCI bus control and changes output enable from ENABLE to
DISABLE.
Figure
2-7. Understanding the latency between the PCI bus and the IP core's Local Master
Table 2-11
31
Description
gives a clock-by-clock description of the basic 32-
Functional Description
PCI IP Core User’s Guide