PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 92

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-33. 32-bit Target Single Read Transaction with a 64-bit Local Interface
The 64-bit memory write transaction is very similar to the 32-bit target write transaction with additional PCI signals
required for 64-bit signaling.
CLK
1
2
3
4
5
6
7
8
9
Turn around
Turn around
PCI Data
Address
Phase
Data 1
Data 2
Wait
Wait
Wait
Idle
The master asserts framen and drives ad[31:0] and cben[3:0].
The master tri-states the ad lines and drives the first byte enables (Byte Enable 1). If the master is
ready to receive data, it asserts irdyn.
The Core starts to decode the address and command. The Core drives the lt_address_out to
the back-end.
If there is an address match, the Core drives the bar_hit signals to the back-end. The back-end
can use the bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on clock after bar_hit. If the
back-end will be ready to put data out on the next cycle, it can assert lt_rdyn.
Quad Word Aligned
With lt_rdyn asserted on the previous cycle, the local interface asserts lt_ldata_xfern. The
back-end drives the first DWORD (Data 1) on l_ad_in[31:0].
Double Word Aligned
With lt_rdyn asserted on the previous cycle, the local interface asserts lt_hdata_xfern. The
back-end drives the first DWORD (Data 1) on l_ad_in[63:32].
With trdyn and irdyn asserted Data 1 is placed on ad[31:0]
Quad Word Aligned
The Core de-asserts lt_ldata_xfern. If irdyn is asserted on the previous cycle, the Core
asserts lt_hdata_xfern to the back-end. With lt_hdata_xfern de-asserted the previous
cycle, the back-end does not increment the address counter and holds the QWORD (Data 2) on
l_ad_in[63:0].
Double Word Aligned
With lt_rdyn asserted during the previous two cycles, the burst cycle starts, so the Core asserts
trdyn and puts Data 1 on ad since the initial address is DWORD aligned. Notice that the lower
DWORD from l_ad_in[31:0] is discarded.
The Core de-asserts lt_hdata_xfern. If both irdyn and lt_rdyn are asserted on the previ-
ous cycle, the Core asserts lt_ldata_xfern to the back-end. With lt_hdata_xfern asserted
the previous cycle, the back-end can increment the address counter and put the next QWORD
(Data 2) on l_ad_in[31:0].
The Core keeps trdyn asserted and puts Data 2 on ad[31:0].
The master relinquishes control of framen and cben[3:0]. It de-asserts irdyn if both trdyn
and irdyn were asserted last cycle.The Core relinquishes control of ad[31:0]. It de-asserts
both devseln and trdyn if both trdyn and irdyn were asserted last cycle.
The Core relinquishes control of devseln and trdyn.The Core also signals to the back-end that
the transaction is complete by clearing bar_hit. The Core de-asserts lt_data_xfern.
Figure 2-29
and
Table 2-34
92
show a basic 64-bit write transaction.
Description
Functional Description
PCI IP Core User’s Guide