PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 130

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Retry
A Retry may be necessary if the PCI IP core cannot assert the trdyn signal within the maximum number of clock
cycles defined by the PCI Local Bus Specification, Revision 3.0. A Retry occurs if lt_rdyn is not asserted before
lt_disconnectn is asserted. A Retry can also occur if the PCI IP core does not assert lt_rdyn within 16 clocks
after the assertion of framen.
Below is a list of the reasons for a Retry.
• Target is very slow to respond to complete first data phase
• Snoop hit occurs on modified cache line
• Resource is busy
Figure 2-48. 32-bit Target Retry for Read Transaction
lt_disconnectn
lt_addressout
lt_data_xfern
l_ad_in[31:0]
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
framen
lt_r_nw
lt_rdyn
stopn
irdyn
trdyn
par
clk
1
Don’t care
Command
Address
Bus
0x00
2
Figure 2-48
Address
Parity
3
and
4
Byte Enable 1
Table 2-54
5
130
Don’t care
show a Retry on a read transaction.
Don’t care
6
0x01
Don’t care
Address
7
Don’t care
8
Functional Description
9
PCI IP Core User’s Guide
10
0x00
11