PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 72

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-25. 32- Bit Dual Address Cycle – Read Transaction (Continued)
CLK
10
6
7
8
9
Turn around
Address
Address
Phase
Data 1
Data 2
High
Low
The Core asserts framen and the local master de-asserts lm_req32n when the previous
lm_status[3:0] was ‘Address Loading’ and if it doesn’t want to request another PCI bus trans-
action.
Since lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI start-
ing address on ad[31:0] and the PCI command (DAC) on cben[3:0]. On the same cycle, it
keeps lm_status[3:0] as ‘Address Loading’ for the Dual Address Cycle.
Local master provides higher address on l_ad_in[31:0].
lm_burst_cnt gets the value of the burst length.
The Core de-asserts reqn when framen was asserted but lm_req32n was de-asserted on the
previous cycle.
The Core keeps framen to start transaction.
Since lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI
higher starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle,
it outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data
phases.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides the byte enables on lm_cben_in[3:0]. Asserting lm_rdyn also
means the local master is ready to read. If it is not ready to read data, it keep lm_rdyn de-
asserted until it is ready.
The Core de-asserts lm_gntn to follow gntn.
The target asserts to indicate it acknowledges the 32-bit transaction.
The Core tri-states the ad[63:0] lines and drives the byte enables (Byte Enable 1). Since
lm_rdyn was asserted on the previous cycle, it asserts irdyn to indicate it is ready to read data.
Because the Core performs the burst transactions, it keeps framen asserted.
The target asserts trdyn and puts Data 1 on ad[31:0].
With lm_rdyn asserted on the previous cycle, the Core keeps irdyn asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the local master is ready to read the first DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle.
Since the previous data phase was completed, the Core transfers Data 1 on l_data_out[31:0]
and decreases the lm_burst_cnt.
If both trdyn and lm_rdyn were asserted on the previous cycle, the Core asserts
lm_data_xfern to the local master to signify Data 1 are available on l_data_out[31:0]. With
lm_data_xfern asserted, the local master can safely read Data 1 and increment the address
counter.
If the local master keeps lm_rdyn asserted on the previous cycle, the master keeps irdyn
asserted.
The Core keeps framen asserted to the target to signify the burst continues.
If the target is still ready to provide data, it keeps trdyn asserted and drives the next DWORD
(Data 2) on ad[31:0].
If the local master is ready to read the next DWORD, it keeps lm_rdyn asserted.
Since both irdyn and trdyn are asserted, the second data phase is completed on this cycle.
72
Description
Functional Description
PCI IP Core User’s Guide