PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 23

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Bar Mapped to I/O Space
When selecting the amount of required I/O space for a BAR, the amount is saved to the BAR0-BAR5 parameters in
its 2’s complement form. Bits 0 and 1 of an I/O BAR describe the attributes of the BAR and do not change.
Figure 2-6
Figure 2-6. I/O Base Address Register
Table 2-8. I/O Base Address Register
Cache Line Size
The Cache Line Size register is an 8-bit read/write register, located at 0Ch. It specifies the Cache Line Size in Dou-
ble Words (DWORDs). During a reset the register is set to 00h. This register is output to local interface as
cache[7:0].
Latency Timer
The Latency Timer register is an eight-bit read/write or read only register, located at byte address 0Dh. It specifies
the Master Latency Timer value for a PCI Master on the PCI bus. During reset the register is set to 00h.
CardBus CIS Pointer
The CardBus CIS Pointer is a read-only, 32-bit register at location 28h in the Configuration Space. The
CIS_POINTER parameter determines the value of the register. For more information on the CardBus CIS Pointer,
refer to the CardBus specification.
Subsystem Vendor ID
The Subsystem Vendor ID is a 16-bit, read-only field and is used to further identify the manufacturer of the expan-
sion board or subsystem. The SUBSYSTEM_VENDOR_ID parameter determines the value of the Subsystem Vendor
ID register. The PCI SIG assigns the Vendor ID to ensure uniqueness. Contact PCI SIG (www.pcisig.org) to attain
a unique Subsystem Vendor ID.
Subsystem ID
The Subsystem ID is a 16-bit, read-only field and is used to further identify the particular device. This field is
defined by the manufacturer and is used to uniquely identify products or models. The SUBSYSTEM_ID parameter
determines the value of this register.
Location
2-31
Bit
0
1
and
Memory/I/O space Indicator indicates whether the base address is mapped to I/O or memory space. A 0 indi-
cates mapping to the memory space. The value of this bit is set by bit 0 of the BAR0-BAR5 parameters.
Bit 1 is reserved and hardwired to 0. This bit is read only.
Bits 2-31 are read/write to hold the memory address and are initialized by the BAR0-BAR5 parameters.
Table 2-8
describe the configuration of a BAR for I/O space.
Reserved
Memory/IO Space Indicator
31
23
Description
1
Functional Description
0
PCI IP Core User’s Guide