PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 87

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
64-Bit PCI Target with a 64-Bit Local Bus
This section discusses read and write transactions for a PCI IP core, operating as a target, configured with a 64-bit
PCI bus and a 64-bit local bus. All 64-bit PCI devices are required by the PCI Specification to handle both 64-bit
and 32-bit applications. The 32-bit transactions, described in the 32-Bit PCI Target with a 32-Bit Local Bus Memory
Transactions section, are similar to a 32-bit transaction for the 64-bit PCI IP core configuration with the exception
that when the 64-bit Core responds to a 32-bit transaction the upper 32 bits of the data bus should be ignored.
The 64-bit memory read transaction is similar to the 32-bit target read transaction with additional PCI signals
required for 64-bit signaling.
Figure 2-26. 64-Bit Target Single Read Transaction with a 64-Bit Local Interface
lt_command_out[3:0]
lt_cben_out[3:0]
lt_cben_out[7:4]
lt_64bit_transn
lt_address_out
lt_hdata_xfern
l_ad_in[63:32]
lt_ldata_xfern
l_ad_in[31:0]
Figure 2-27
bar_hit[5:0]
lt_accessn
ad[63:32]
cben[3:0]
cben[7:4]
ad[31:0]
devseln
ack64n
lt_r_nw
framen
req64n
lt_rdyn
par64
trdyn
irdyn
par
clk
1
Don't care
Don't care
Don't care
Don't care
Command
Address
Bus
Don't care
Don't care
and
0x00
2
Don't care
Table 2-31
Address
Parity
Don't care
Don't care
3
4
87
illustrate a basic 64-bit read transaction.
Byte Enable 1
Byte Enable 2
Don't care
Don't care
5
Bus Command
Byte Enable 1
Byte Enable 2
Don't care
Don't care
Address
Data 1
Data 2
0x01
6
Data 1
Data 2
7
Don't care
Don't care
Parity 1
Parity 2
Data
Data
8
Don't care
Don't care
0x00
Functional Description
9
PCI IP Core User’s Guide