PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 15

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Local Interface Signals
The Local Interface provides all the necessary address and control signals to respond to and initiate transactions
associated with the PCI bus. Command and status information are also available at the Local Interface, so the
back-end application logic can essentially monitor the PCI bus.
are divided into three different categories: Local Bus Signals, Local Target Bus signals and Local Master Bus sig-
nals.
The Local Bus Signals are shared between the Local Master Interface and Local Target Interface. These signals
are typically denoted with an “l_”. The Local Target Bus signals are used by the Local Target Interface and are
denoted using “lt_”. The Local Master Bus signals are used by the Local Master interface and are denoted using
“lm_”.
Table 2-3. PCI IP Core Signals
Table 2-4. Local Interface Signals
PCI Error Reporting
perrn
serrn
PCI Interrupt
intan
PCI Bus Arbitration
reqn
gntn
PCI 64-Bit Extension
ad[63:32
]
cben[7:4
]
par64
req64n
ack64n
1. Shaded rows apply to 64-bit applications.
Local Address and Data
l_ad_in[31:0]
l_data_out[31:0]
lt_address_out [31:0]
lt_cben_out[3:0]
lt_command_out[3:0]
lm_cben_in[3:0]
Name
Name
s/t/s
s/t/s
s/t/s
I/O
o/d
o/d
out
t/s
t/s
t/s
in
Polarity
low
low
low
low
low
low
low
—
—
—
Data parity error is used to report parity errors in the data phase.
System error is used to indicate catastrophic errors.
Interrupt A is used to request an interrupt.
Request for the use of PCI bus.
Grant the master’s access to PCI bus.
The upper 32 bits of multiplexed address and data bus.
The upper, multiplexed command and byte enable signals for 64-bit applications.
The par64 signal generates even parity for ad[63:32] and cben[7:4] signals.
Used by the master to request a 64-bit data transaction.
Signal used to indicate the acknowledgement of a request for 64-bit data transaction.
out
out
out
out
I/O
in
in
1
(Continued)
1
Polarity
low
low
—
—
—
—
Local address/data input. The address input is used in Master Read/Write
transactions, and the data input is used for master write/target read transac-
tions
Local Data output. Local side lower DWORD data output for a master read
or a target write.
The local address bus for target read and write. This bus indicates the start
address of the transaction. The bus, lt_address_out [31:0], is latched
one clock after the framen signal is asserted on each transaction and
remains unchanged until the next transaction.
The local byte enables for target read and write. The lt_cben_out[3:0]
determine which byte lanes of l_data_out[31:0] or l_ad_in[31:0]
carry meaningful data.
The lt_command_out[3:0] latches the command information during the
address phase of a PCI cycle. It indicates the PCI bus command for the cur-
rent cycle (refer to
Local master command and byte enables.
15
Table
Table 2-4
Description
2-1).
contains the Local Interface signals that
Description
Functional Description
PCI IP Core User’s Guide