PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 143

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Chapter 4:
IP Core Generation
This chapter provides information on how to generate the PCI IP core using the Diamond or ispLEVER software
IPexpress tool, and how to include the core in a top-level design.
Licensing the IP Core
An IP core- and device-specific license is required to enable full, unrestricted use of the PCI IP core in a complete,
top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at:
http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm
Users may download and generate the PCI IP core and fully evaluate the core through functional simulation and
implementation (synthesis, map, place and route) without an IP license. The PCI IP core also supports Lattice’s IP
hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware
for a limited time (approximately four hours) without requiring an IP license. See
“Hardware Evaluation” on
page 148
for further details. However, a license is required to enable timing simulation, to open the design in the
Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evaluation timeout
limitation.
Getting Started
The PCI IP core is available for download from the Lattice IP Server using the IPexpress tool. The IP files are auto-
matically installed using ispUPDATE technology in any customer-specified directory. After the IP core has been
installed, the IP core will be available in the IPexpress GUI dialog box shown in
Figure 4-1.
The IPexpress tool GUI dialog box for the PCI IP core is shown in
Figure
4-1. To generate a specific IP core config-
uration the user specifies:
• Project Path – Path to the directory where the generated IP files will be located.
• File Name – “username” designation given to the generated IP core and corresponding folders and files.
• (Diamond) Module Output – Verilog or VHDL.
• (ispLEVER) Design Entry Type – Verilog HDL or VHDL.
• Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3,
etc.). Only families that support the particular IP core are listed.
• Part Name – Specific targeted part within the selected device family.
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PCI IP Core User’s Guide