PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 51

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
Burst Read and Write Master Transactions
Burst read and write transactions to memory addresses are used to achieve the high throughput associated with
the PCI bus. The PCI IP core supports the zero-wait state and burst data transfers for the following commands:
• Memory Read
• Memory Write
• Memory Read Multiple
• Dual Address Cycle
• Memory Read Line
• Memory Write and Invalidate
The burst data transfers are described based on the different PCI and Local bus configurations supported by the
PCI IP core. Although the fundamentals of burst data transfers are similar for all PCI IP core configurations, differ-
ent bus configurations require slightly different Local Master Interface signaling. The PCI IP core does not execute
burst cycles for Configuration Space or I/O space accesses. Refer to the following sections for more information on
bursting with specific PCI IP core configurations:
• 32-Bit PCI Master and a 32-Bit Local Bus
• 64-Bit PCI Master with a 64-Bit Local Bus
• 32-Bit PCI Master with a 64-Bit Local Bus
32-Bit PCI Master and a 32-bit Local Bus
The following section discusses read and write burst data transfers for a PCI IP core configured with a 32-bit PCI
bus and a 32-bit Local bus.
Figure 2-15
and
Table 2-19
show a 32-bit burst data transfer during a read transaction.
The figure illustrates how the PCI interface correlates to the Local Master Interface. The table gives a clock-by-
clock description of each event that occurs in the figure.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide