PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 109

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-42. 64-bit Target Burst Write Transaction with a 64-bit Local Interface
IPUG18_09.2, November 2010
32-Bit PCI Target with a 64-bit Local Bus
The following discusses read and write transactions for a PCI IP core configured with a 32-bit PCI bus and a 64-bit
local bus. In order to present a full 64 bits of data to the Local Interface, two PCI data phase are required. Likewise
retrieving 64 bits of data from the Local Interface, two PCI data phases are required.
The 32-bit PCI transaction, as described in the 32-Bit PCI Bus and 32-Bit Local Bus section, looks similar to these
transactions; however, the data is handled differently at the Local Interface. When the 32-bit target core responds
to a 32-bit burst transaction, the upper 32 bits of the Local data bus should be ignored or return 0’s.
With a 64-bit back-end, it is assumed that the address counter needs to increment only by a Quad Word (QWORD)
(8 bytes), so the local back-end control latches the complete QWORD and routes the proper DWORD to the PCI
data bus. The lt_ldata_xfern and lt_hdata_xfern signals specify which DWORD is transferred.
CLK
1
2
3
4
5
6
7
8
9
Data 1 and 2 The trdyn signal is asserted since lt_rdyn was asserted on the previous cycle.
Data 3 and 4
Data 5 and 6
Turn around
PCI Data
Address
Phase
Wait
Wait
Wait
Idle
The PCI master asserts framen and drives ad[31:0] and cben[3:0]. It requests a 64-bit trans-
action by asserting req64n with framen.
The PCI master drives the first byte enables (Byte Enable 1 and 2) on cben[7:0]. If the PCI mas-
ter is ready to write data, it asserts irdyn and drives the first QWORD (Data 1 and 2) on
ad[63:0].The Core starts to decode the address and command. The target drives
lt_address_out to the back-end. The lt_64bit_trans signal is driven high to signal the
back-end application that a 64-bit transaction has been requested.
If there is an address match, the Core drives the bar_hit signals to the back-end application. It
can use bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on the clock after bar_hit. If
the back-end is ready to write data in two cycles it can assert lt_rdyn. The PCI IP core acknowl-
edges the 64-bit transaction by asserting ack64n.
If the back-end keeps lt_rdyn asserted on the previous cycle, the Core keeps trdyn asserted
and puts Data 1 and 2 on lt_data_out.If both irdyn and trdyn are asserted on the previous
cycle, the master drives the next byte enables (Byte Enable 3 and 4) on cben[7:0]. If the PCI
master is still ready to write data, it keeps irdyn asserted and drives the next QWORD (Data 3
and 4) on ad[63:0]. If both irdyn and lt_rdyn are asserted on the previous cycle, the Core
asserts lt_ldata_xfern and lt_hdata_xfern to the back-end to signify Data 1 and 2 is valid.
With lt_ldata_xfern and lt_hdata_xfern asserted the back-end can safely write Data 1
and 2 and increment the address counter.
If the back-end keeps lt_rdyn asserted on the previous cycle, the Core keeps trdyn asserted
and puts Data 3 and 4 on lt_data_out. If both irdyn and trdyn are asserted on the previous
cycle, the PCI master drives the next byte enables (Byte Enable 5 and 6) on cben[7:0]. If it is still
ready to write data, it keeps irdyn asserted and drives the next QWORD (Data 5 and 6) on
ad[63:0]. The master signals the end of the burst when it de-asserts framen and req64n. If
both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps lt_ldata_xfern
and lt_hdata_xfern asserted to the back-end to signify Data 3 and 4 is valid. With
lt_ldata_xfern and lt_hdata_xfern asserted the back-end can safely write Data 3 and 4
and increment the address counter. There is no signal yet to the back-end that the burst is over.
If the back-end keeps lt_rdyn asserted the previous cycle, the target puts Data 5 and 6 on
lt_data_out.If both irdyn and trdyn are asserted on the previous cycle, the master relin-
quishes control of framen, req64n, ad[63:0] and cben[7:0]. It also de-asserts irdyn if both
trdyn and irdyn were asserted on the last cycle. If both irdyn and lt_rdyn were asserted on
the previous cycle, the target keeps lt_ldata_xfern and lt_hdata_xfern asserted to the
back-end to signify Data 5 and 6 is valid. With lt_ldata_xfern and lt_hdata_xfern asserted
the back-end can safely write Data 5 and 6 and increment the address counter. It de-asserts
devseln, ack64n and trdyn if both trdyn and irdyn were asserted last cycle.
The Core signals to the back-end that the transaction is complete by clearing bar_hit. It also de-
asserts lt_ldata_xfern and lt_hdata_xfern.The target relinquishes control of devseln,
ack46n and trdyn.
109
Description
Functional Description
PCI IP Core User’s Guide