PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 30

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
Local Bus Interface
Target Operation
Initially, the local target is idle. A valid transaction in the PCI bus is indicated to the local bus side by the assertion of
lt_accessn signal. At this time either the bar_hit, new_cap_hit or exprom_hit signal indicates whether a
BAR or New Capabilities register is selected, and lt_command_out indicates the current PCI command. If the
command is Special Cycle, then no BAR is selected, otherwise the selected BAR needs to prepare the next pro-
cess.
For a Memory Read command, local target puts data on lt_ad_in and asserts lt_rdyn to indicate data on
l_ad_in is valid. The core will read the data and assert lt_data_xfern after lt_rdyn is active. When the
transaction is burst read, the core will continue to keep asserting lt_data_xfern at subsequent clocks and read
data on l_ad_in if the local side does not insert wait cycle(s).
For a Memory Write command, local target asserts lt_rdyn to indicate that it is ready to receive data on
l_data_out. The core will write data on l_data_out and assert lt_data_xfern to indicate valid data on
l_data_out. Local target should read the data on l_data_out.
When the local target bus width is 64 bits, the signals lt_ldata_xfern and lt_hdata_xfern are used
together instead of lt_data_xfern. For 32-bit data width, only lt_ldata_xfern is used. For 64-bit data width,
lt_ldata_xfern and lt_hdata_xfern are used together. The signal lt_ldata_xfern applies to the lower
32-bit data, lt_hdata_xfern applies to the upper 32 bits of data.
A target transaction is ended when lt_accessn becomes inactive. At this time, bar_hit, new_cap_hit and
exprom_hit are all deasserted.
When a 32-bit BAR is hit, only the following local bus signals are used:
• l_ad_in[31:0], l_data_out[31:0], lt_cben_out[3:0] and lt_ldata_xfern.
and the following signals are not used:
• l_ad_in[63:32], l_data_out[63:32], lt_cben_out[7:4] and lt_hdata_xfern.
Master Operation
Local master starts a transaction request by asserting lm_req32n or lm_req64n when lm_status is in “Bus
Termination” state. For a 32-bit transaction request, lm_req32n is asserted and lm_req64n is a “don't care”. For
a 64-bit transaction, lm_req64n is asserted and lm_req32n is de-asserted. To minimize latency, the local master
should issue the valid address, command and burst length on l_ad_in, lm_cben_in[3:0] and
lm_burst_length respectively during the same clock cycle that lm_req32n or lm_req6n is asserted. Once
PCI bus grants the bus, lm_gntn is asserted to indicate local master to continue with next process. Then local
master works with lm_status. lm_req32n and lm_req64n should be deasserted right after lm_status is in
“Address Loading” state, unless Fast Back-to-Back is intended. A normal transaction sequence of status starts
from “Bus Termination” to “Address Loading” to “Bus Transaction” and ends with “Bus Termination”. During “Bus
Transaction”, local master reads or writes data based on lm_data_xfern signal.
When the local master bus width is 64-bit, lm_ldata_xfern and lm_hdata_xfern are used instead of
lm_data_xfern. For 32-bit data width BAR, only lm_ldata_xfern is used. For 64-bit data width BAR,
lm_ldata_xfern and lm_hdata_xfern are used together. The signal lm_ldata_xfern applies to the lower
32 bits of data, lm_hdata_xfern applies to the upper 32 bits of data.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide