PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 95

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-30. Basic Configuration Read
Table 2-35. Basic Configuration Read
CLK
1
2
3
4
5
6
7
cben[3:0]
ad[31:0]
devseln
framen
stopn
trdyn
irdyn
idsel
Turn around
Turn around
par
clk
PCI Bus
Address
Phase
Data 1
Wait
Wait
Idle
1
Command
Address
ready to receive data, it asserts irdyn.The Core starts to decode the address and command.
The address decode continues.
If the devsel_timing is set to slow, the Core asserts devseln. The Core is ready to put data out on
the next cycle.
The data cycle starts as the target Core trdyn and puts Data 1 on ad. The Core also asserts
stopn to ensure the configuration transaction is single data phase.
The master relinquishes control of framen and cben[3:0]. It de-asserts irdyn if both trdyn
and irdyn were asserted during the last cycle.
The Core relinquishes control of ad[31:0]. It de-asserts both devseln, trdyn and stopn if
both trdyn and irdyn were asserted during the last cycle.
The master asserts framen and idsel. It drives the configuration address and Configuration
Read command. The configuration address is ad[1:0] = 00 (type zero access); ad[7:2] = con-
figuration DWORD address; ad[10:8] = function number; and ad[31:11] = unused.
The master tri-states ad[31:0]and drives the first byte enable (Byte Enable 1). If the master is
The Core relinquishes control of devseln, trdyn and stopn.
Bus
2
Address
Parity
3
Don’t care
Enable 1
4
Byte
Don’t care
95
5
Description
Data 1
6
Data Parity
1
7
Functional Description
PCI IP Core User’s Guide
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