PCI-T64-O4-N2 Lattice, PCI-T64-O4-N2 Datasheet - Page 16

• Manufacturer Part Number: PCI-T64-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Target 64B
• Manufacturer: Lattice

Specifications of PCI-T64-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Table 2-4. Local Interface Signals
Local 64-Bit Extension
l_ad_in[63:32]
l_data_out[63:32]
lt_address_out [63:32]
lt_cben_out[7:4]
lt_ldata_xfern
lt_hdata_xfern
lt_64bit_transn
lm_ldata_xfern
lm_hdata_xfern
lm_64bit_transn
lm_cben_in[7:4]
Local Interrupt
l_interruptn
Config Register
cache[7:0]
command[9:0]
status[5:0]
Name
out
out
out
out
out
out
out
out
out
out
out
out
I/O
in
in
in
1
Polarity
(Continued)
low
low
low
low
low
low
low
low
low
—
—
—
—
—
—
Local address/data input. The address input is used in Master Read/Write
transactions, and the data input is used for master write/target read transac-
tions.
Local Data output. Local side upper DWORD data output for a master read
or a target write.
The local address bus for target read and write. This bus is valid only for
64bit address bar. The 64-bit combined signal lt_address_out [63:0]
indicates the start address of the transaction. The high 32bit of the bus,
lt_address_out[63:32], is latched two clock cycles after the framen
signal is asserted on each transaction (only for dual address cycle) and
remains unchanged until the next transaction.
The local byte enables for 64-bit target read and write. The
lt_cben_out[7:4] determine which byte lanes of
l_data_out[63:32] or l_ad_in[63:32] carry meaningful data.
This signal works same as lt_data_xfern. It applies to lower DWORD
when local bus is 64bit.
This signal works same as lt_data_xfern. It applies to upper DWORD
when local bus is 64bit.
Signal to the local target that a 64-bit read or write transaction is underway
on pci bus.
This signal works same as lm_data_xfern. It applies to lower DWORD
when local bus is 64bit.
This signal works same as lm_data_xfern. It applies to upper DWORD
when local bus is 64bit.
Signal to the local master that a 64-bit read or write transaction is underway
on PCI bus.
Local master byte enables.
The local side interrupt request indicates that the Local Interface is request-
ing an interrupt. This signal asserts the PCI side interrupt signal, intan, if
interrupts are enabled in the Configuration Space.
The cache signal indicates the cache length in the cache registers defined
in the Configuration Space
Command register bits from the Configuration Space.
Bit 0 - I/O space enable, Command[0]
Bit 1 - Memory space enable, Command[1]
Bit 2 - Master enable, Command[2]
Bit 3 - Special cycles enable, Command[3]
Bit 4 - Memory write and invalidate enable, Command[4]
Bit 5 - VGA Palette Snoop, Command[5]
Bit 6 - Parity Error Response, Command[6]
Bit 7 - Reserved
Bit 8 - SERR# enable, Command[8]
Bit 9 - Fast back-to-back enable, Command[9]
Status register bits from the Configuration Space.
Bit 0 - Master Data Parity Error, Status[8]
Bit 1 - Signaled Target Abort, Status[11]
Bit 2 - Received Target Abort, Status[12]
Bit 3 - Received Master Abort, Status[13]
Bit 4 - Signaled System Error with SERR#, Status[14]
Bit 5 - Detected Parity Error, Status[15]
16
Description
Functional Description
PCI IP Core User’s Guide